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    DEVICE, SYSTEM AND METHOD TO IDENTIFY A SOURCE OF DATA POISONING
    5.
    发明申请
    DEVICE, SYSTEM AND METHOD TO IDENTIFY A SOURCE OF DATA POISONING 有权

    公开(公告)号：US20210248026A1

    公开(公告)日：2021-08-12

    申请号：US17153337

    申请日：2021-01-20

    Applicant: Intel Corporation

    Inventor： Mohan J. Kumar ,  Theodros Yigzaw ,  Murugasamy Nachimuthu ,  Ashok Raj ,  Jose Vargas

    IPC: G06F11/07

    Abstract: Techniques and mechanisms for a processor to efficiently identify a circuit resource as being a source of data poisoning. In an embodiment, metadata is communicated, in association with a communication of poisoned data to which the metadata pertains, to a first circuit block of a processor. The metadata indicates a poisoned state of the data, wherein the metadata identifies a second circuit block—which is included in or coupled to the processor—as being a poisoner of the data. Based on the metadata, the first circuit block generates a fault message which identifies the second circuit block as the poisoner of the data. In another embodiment, the processor further comprises the second circuit block, which poisons the data (based on the detection of an error condition) by providing in the metadata a unique identifier which is assigned to the second circuit block.

    Apparatus and method to identify the source of an interrupt
    6.
    发明授权
    Apparatus and method to identify the source of an interrupt 有权

    公开(公告)号：US11048512B1

    公开(公告)日：2021-06-29

    申请号：US16833598

    申请日：2020-03-28

    Applicant: Intel Corporation

    Inventor： Ashok Raj ,  Andreas Kleen ,  Gilbert Neiger ,  Beeman Strong ,  Jason Brandt ,  Rupin Vakharwala ,  Jeff Huxel ,  Larisa Novakovsky ,  Ido Ouziel ,  Sarathy Jayakumar

    IPC: G06F9/50 ,  G06F9/30 ,  G06F15/80 ,  G06F9/48

    Abstract: An apparatus and method for processing non-maskable interrupt source information. For example, one embodiment of a processor comprises: a plurality of cores comprising execution circuitry to execute instructions and process data; local interrupt circuitry comprising a plurality of registers to store interrupt-related data including non-maskable interrupt (NMI) data related to a first NMI; and non-maskable interrupt (NMI) processing mode selection circuitry, responsive to a request, to select between at least two NMI processing modes to process the first NMI including: a first NMI processing mode in which the plurality of registers are to store first data related to a first NMI, wherein no NMI source information related to a source of the NMI is included in the first data, and a second NMI processing mode in which the plurality of registers are to store both the first data related to the first NMI and second data comprising NMI source information indicating the NMI source.

    Determine when an error log was created
    7.
    发明授权
    Determine when an error log was created 有权

    公开(公告)号：US10430267B2

    公开(公告)日：2019-10-01

    申请号：US15206853

    申请日：2016-07-11

    Applicant: INTEL CORPORATION

    Inventor： Ashok Raj ,  Narayan Ranganathan

    IPC: G06F11/00 ,  G06F11/07 ,  G06F11/14

    Abstract: A computing system can include a machine check counter (MCC) including a current value. The current value indicates a system reboot resetting hardware of the computing system. The machine check counter includes a model specific register including a counter indicating the current value, the current value to be incremented upon the system reboot.

    Management of Processor Performance Based on User Interrupts
    8.
    发明申请
    Management of Processor Performance Based on User Interrupts 审中-公开

    公开(公告)号：US20190213153A1

    公开(公告)日：2019-07-11

    申请号：US15864290

    申请日：2018-01-08

    Applicant: Intel Corporation

    Inventor： Jacob Jun Pan ,  Ashok Raj ,  Srinivas Pandruvada

    IPC: G06F13/24

    Abstract: In an embodiment, a processor for performance state adjustment includes a plurality of processing engines (PEs), a power control unit, and an input/output memory management unit (IOMMU). The IOMMU is to determine a destination PE for a user interrupt based on mapping data of the IOMMU, and to send a notification of the user interrupt to the power control unit. The notification indicates the destination PE for the user interrupt. The power control unit is to adjust a performance state of the destination PE in response to the notification of the user interrupt. Other embodiments are described and claimed.

    Handling of error prone cache line slots of memory side cache of multi-level system memory
    9.
    发明授权
    Handling of error prone cache line slots of memory side cache of multi-level system memory 有权

    公开(公告)号：US10185619B2

    公开(公告)日：2019-01-22

    申请号：US15087797

    申请日：2016-03-31

    Applicant: INTEL CORPORATION

    Inventor： Theodros Yigzaw ,  Ashok Raj ,  Robert Swanson ,  Mohan J. Kumar

    IPC: G06F11/07 ,  G06F12/0804

    Abstract: An apparatus is described that includes memory controller logic circuitry to interface with a memory side cache of a multi-level system memory. The memory controller logic circuitry includes error tracking circuitry to track errors of cache line slots in the memory side cache. The memory controller logic circuitry also comprises faulty list circuitry to store identifiers of faulty cache line slots that are deemed to be excessively error prone. The memory controller logic circuitry is to declare a miss in the memory side cache for requests that map to cache line slots identified in the faulty list.

    Instruction and Logic for Machine Check Interrupt Management
    10.
    发明申请
    Instruction and Logic for Machine Check Interrupt Management 有权
    机器检查中断管理指令和逻辑

    公开(公告)号：US20160092220A1

    公开(公告)日：2016-03-31

    申请号：US14498092

    申请日：2014-09-26

    Applicant: Intel Corporation

    Inventor： Ashok Raj ,  Mohan J. Kumar

    IPC: G06F9/30

    CPC classification number: G06F9/30072 ,  G06F9/30076 ,  G06F9/30109 ,  G06F9/3861

    Abstract: A processor includes a front end including a decoder to decode an instruction, a scheduler to assign execution of the instruction to a core, and a core to execute the instruction. The instruction specifies that interrupts such as corrected machine check interrupts are to be selectively suppressed. The processor further includes an error handling unit including logic to determine that an interrupt caused by an error is to be created and that an error consumer has requested interrupt notification. The error handling unit further includes logic to, based on the instruction specifying that interrupts are to be selectively suppressed, send the interrupt to a producer that issued the instruction rather than the error consumer.

    Abstract translation: 处理器包括前端，其包括用于解码指令的解码器，向核心分配指令执行的调度器以及执行指令的核心。 该指令指定要选择性地抑制诸如校正机器检查中断之类的中断。 该处理器还包括错误处理单元，其包括用于确定由错误引起的中断将被创建并且错误消费者已经请求中断通知的逻辑。 错误处理单元还包括基于指定要被选择性地抑制中断的指令的逻辑，将中断发送给发出指令而不是错误消费者的生产者。

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