公开(公告)号：US20220091852A1

公开(公告)日：2022-03-24

申请号：US17028387

申请日：2020-09-22

Applicant: Intel Corporation

Inventor： Saurabh Gupta ,  Niranjan Kumar Soundarajan ,  Sreenivas Subramoney ,  Ragavendra Natarajan

IPC: G06F9/38 ,  G06F9/30

Abstract: Methods and apparatus relating to Instruction Set Architecture (ISA) and/or microarchitecture for early pipeline re-steering using load address prediction to mitigate branch misprediction penalties are described. In an embodiment, decode circuitry decodes a load instruction and Load Address Predictor (LAP) circuitry issues a load prefetch request to memory for data for a load operation of the load instruction. Compute circuitry executes an outcome for a branch operation of the load instruction based on the data from the load prefetch request. And re-steering circuitry transmits a signal to cause flushing of data associated with the load instruction in response to a mismatch between the outcome for the branch operation and a stored prediction value for the branch. Other embodiments are also disclosed and claimed.

公开(公告)号：US10579414B2

公开(公告)日：2020-03-03

申请号：US15477064

申请日：2017-04-01

Applicant: Intel Corporation

Inventor： Niranjan K. Soundararajan ,  Saurabh Gupta ,  Sreenivas Subramoney ,  Rahul Pal ,  Ragavendra Natarajan ,  Daniel Deng ,  Jared W. Stark ,  Ronak Singhal ,  Hong Wang

IPC: G06F9/38 ,  G06F9/46

Abstract: Embodiments of apparatuses, methods, and systems for misprediction-triggered local history-based branch prediction are described. In one embodiments, an apparatus includes a current pattern table and a local pattern table. The current pattern table has a plurality of entries, each entry in which to store a plurality of pattern lengths of a current pattern of one of a plurality of branch instructions. The local pattern table is to provide a first branch prediction based on the current pattern.