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    Selective use of branch prediction hints
    1.
    发明授权
    Selective use of branch prediction hints 有权

    公开(公告)号：US12282778B2

    公开(公告)日：2025-04-22

    申请号：US18479974

    申请日：2023-10-03

    Applicant: Intel Corporation

    Inventor： Jared W. Stark ,  Ahmad Yasin ,  Ajay Amarsingh Singh

    IPC: G06F9/38 ,  G06F9/30 ,  G06F12/0804

    Abstract: Embodiments of apparatuses, methods, and systems for selective use of branch prediction hints are described. In an embodiment, an apparatus includes an instruction decoder and a branch predictor. The instruction decoder is to decode a branch instruction having a hint. The branch predictor is to provide a prediction and a hint-override indicator. The hint-override indicator is to indicate whether the prediction is based on stored information about the branch instruction. The prediction is to override the hint if the hint-override indicator indicates that the prediction is based on stored information about the branch instruction.

    Selective use of branch prediction hints
    2.
    发明授权
    Selective use of branch prediction hints 有权

    公开(公告)号：US11809873B2

    公开(公告)日：2023-11-07

    申请号：US17033749

    申请日：2020-09-26

    Applicant: Intel Corporation

    Inventor： Jared W. Stark ,  Ahmad Yasin ,  Ajay Amarsingh Singh

    IPC: G06F9/38 ,  G06F9/30 ,  G06F12/0804

    CPC classification number: G06F9/3842 ,  G06F9/30145 ,  G06F9/3867 ,  G06F12/0804

    Abstract: Embodiments of apparatuses, methods, and systems for selective use of branch prediction hints are described. In an embodiment, an apparatus includes an instruction decoder and a branch predictor. The instruction decoder is to decode a branch instruction having a hint. The branch predictor is to provide a prediction and a hint-override indicator. The hint-override indicator is to indicate whether the prediction is based on stored information about the branch instruction. The prediction is to override the hint if the hint-override indicator indicates that the prediction is based on stored information about the branch instruction.

    CODE PREFETCH INSTRUCTION
    3.
    发明申请
    CODE PREFETCH INSTRUCTION 有权

    公开(公告)号：US20210342134A1

    公开(公告)日：2021-11-04

    申请号：US17033751

    申请日：2020-09-26

    Applicant: Intel Corporation

    Inventor： Ahmad Yasin ,  Lihu Rappoport ,  Jared W. Stark ,  Jeffrey Baxter ,  Israel Diamand ,  Pavel Fridman ,  Ibrahim Hur ,  Nir Tell

    IPC: G06F8/41

    Abstract: Embodiments of apparatuses, methods, and systems for code prefetching are described. In an embodiment, an apparatus includes an instruction decoder, load circuitry, and execution circuitry. The instruction decoder is to decode a code prefetch instruction. The code prefetch instruction is to specify a first instruction to be prefetched. The load circuitry to prefetch the first instruction in response to the decoded code prefetch instruction. The execution circuitry is to execute the first instruction at a fetch stage of a pipeline.

    Apparatus and method for efficient memory renaming prediction using virtual registers
    5.
    发明授权
    Apparatus and method for efficient memory renaming prediction using virtual registers 有权
    使用虚拟寄存器进行高效存储器重命名预测的装置和方法

    公开(公告)号：US09552169B2

    公开(公告)日：2017-01-24

    申请号：US14706936

    申请日：2015-05-07

    Applicant: INTEL CORPORATION

    Inventor： Lihu Rappoport ,  Jared W. Stark ,  Kamil Garifullin ,  Franck Sala ,  Pavel I. Kryukov ,  Stanislav Shwartsman

    IPC: G06F3/06 ,  G06F12/08

    CPC classification number: G06F3/0631 ,  G06F3/06 ,  G06F3/0604 ,  G06F3/0671 ,  G06F9/3826 ,  G06F9/3832 ,  G06F9/3834 ,  G06F9/384 ,  G06F12/0802

    Abstract: A method and apparatus are described for efficient memory renaming prediction using virtual registers. For example, one embodiment of an apparatus comprises: a memory execution unit (MEU) to perform store and load operations to store data to memory and load data from memory, respectively; a plurality of memory rename (MRN) registers assigned to store and load operations, each MRN register to store data associated with a store operation so that the data is available for a subsequent load operation; and at least one MRN predictor comprising a data structure to allocate virtual memory rename (VMRN) registers to each of the MRN registers, the MRN predictor to query the data structure in response to a load and/or store operation using a value identifying the MRN register assigned to the load and/or store operation, respectively, to determine a current VMRN register associated with the load and/or store operation.

    Abstract translation: 描述了使用虚拟寄存器进行有效的存储器重命名预测的方法和装置。 例如，设备的一个实施例包括：存储器执行单元（MEU），用于执行存储和加载操作，以分别将存储数据存储到存储器中并从存储器加载数据; 分配给存储和加载操作的多个存储器重命名（MRN）寄存器，每个MRN寄存器存储与存储操作相关联的数据，使得数据可用于后续加载操作; 以及至少一个MRN预测器，其包括用于向每个MRN寄存器分配虚拟存储器重命名（VMRN）寄存器的数据结构，MRN预测器，使用标识MRN的值来响应于负载和/或存储操作来查询数据结构 分配给负载和/或存储操作的寄存器，以确定与负载和/或存储操作相关联的当前VMRN寄存器。

    SELECTIVE USE OF BRANCH PREDICTION HINTS
    6.
    发明公开
    SELECTIVE USE OF BRANCH PREDICTION HINTS 审中-公开

    公开(公告)号：US20240118898A1

    公开(公告)日：2024-04-11

    申请号：US18479974

    申请日：2023-10-03

    Applicant: Intel Corporation

    Inventor： Jared W. Stark ,  Ahmad Yasin ,  Ajay Amarsingh Singh

    IPC: G06F9/38 ,  G06F9/30 ,  G06F12/0804

    CPC classification number: G06F9/3842 ,  G06F9/30145 ,  G06F9/3867 ,  G06F12/0804

    Abstract: Embodiments of apparatuses, methods, and systems for selective use of branch prediction hints are described. In an embodiment, an apparatus includes an instruction decoder and a branch predictor. The instruction decoder is to decode a branch instruction having a hint. The branch predictor is to provide a prediction and a hint-override indicator. The hint-override indicator is to indicate whether the prediction is based on stored information about the branch instruction. The prediction is to override the hint if the hint-override indicator indicates that the prediction is based on stored information about the branch instruction.

    SELECTIVE USE OF BRANCH PREDICTION HINTS
    7.
    发明申请
    SELECTIVE USE OF BRANCH PREDICTION HINTS 有权

    公开(公告)号：US20210342157A1

    公开(公告)日：2021-11-04

    申请号：US17033749

    申请日：2020-09-26

    Applicant: Intel Corporation

    Inventor： Jared W. Stark ,  Ahmad Yasin ,  Ajay Amarsingh Singh

    IPC: G06F9/38 ,  G06F9/30 ,  G06F12/0804

    Abstract: Embodiments of apparatuses, methods, and systems for selective use of branch prediction hints are described. In an embodiment, an apparatus includes an instruction decoder and a branch predictor. The instruction decoder is to decode a branch instruction having a hint. The branch predictor is to provide a prediction and a hint-override indicator. The hint-override indicator is to indicate whether the prediction is based on stored information about the branch instruction. The prediction is to override the hint if the hint-override indicator indicates that the prediction is based on stored information about the branch instruction.

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