公开(公告)号：US20230100693A1

公开(公告)日：2023-03-30

申请号：US17448795

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Saurabh Gupta ,  Ragavendra Natarajan ,  Niranjan K. Soundararajan ,  Jared W. Stark, IV ,  Sreenivas Subramoney

IPC: G06F9/38

Abstract: In an embodiment, a processor may include an execution circuit to execute a plurality of instructions. The processor may also include a prediction circuit to: in response to a detection of a first target instruction in a program, identify a prediction data entry associated with a path history for the first target instruction, the identified prediction data entry to indicate an offset distance from the first target instruction to a predicted next taken branch of the program; and determine the predicted next taken branch of the program based on the offset distance indicated by the identified prediction data entry. Other embodiments are described and claimed.

公开(公告)号：US20190220284A1

公开(公告)日：2019-07-18

申请号：US15870595

申请日：2018-01-12

Applicant: Intel Corporation

Inventor： Saurabh Gupta ,  Rahul Pal ,  Niranjan Soundararajan ,  Ragavendra Natarajan ,  Sreenivas Subramoney

IPC: G06F9/38

CPC classification number: G06F9/3844 ,  G06F9/3806 ,  G06F9/3859 ,  G06F9/3861

Abstract: One embodiment provides an apparatus. The apparatus includes a store direct dependent (SDD) branch prediction circuitry and an SDD management circuitry. The store direct dependent (SDD) branch prediction circuitry is to store an SDD branch table. The SDD branch table is to store at least one record. Each record includes a branch instruction pointer (IP) field, a load IP field, a store IP field, a comparison info field and at least one of a store value field and/or a predicted outcome field. The SDD management circuitry is to populate the SDD branch table at runtime and to override a baseline branch prediction associated with an incoming branch IP with an SDD branch prediction, if the SDD branch table contains a first record populated with the incoming branch IP and at least one of a store value and/or an SDD predicted outcome.

公开(公告)号：US20180285115A1

公开(公告)日：2018-10-04

申请号：US15477064

申请日：2017-04-01

Applicant: Intel Corporation

Inventor： Niranjan K. Soundararajan ,  Saurabh Gupta ,  Sreenivas Subramoney ,  Rahul Pal ,  Ragavendra Natarajan ,  Daniel Deng ,  Jared W. Stark ,  Ronak Singhal ,  Hong Wang

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/46

CPC classification number: G06F9/46 ,  G06F9/3848

Abstract: Embodiments of apparatuses, methods, and systems for misprediction-triggered local history-based branch prediction are described. In one embodiments, an apparatus includes a current pattern table and a local pattern table. The current pattern table has a plurality of entries, each entry in which to store a plurality of pattern lengths of a current pattern of one of a plurality of branch instructions. The local pattern table is to provide a first branch prediction based on the current pattern.

公开(公告)号：US10949208B2

公开(公告)日：2021-03-16

申请号：US16221871

申请日：2018-12-17

Applicant: Intel Corporation

Inventor： Saurabh Gupta ,  Niranjan Soundararajan ,  Ragavendra Natarajan ,  Jared Warner Stark, IV ,  Lihu Rappoport ,  Sreenivas Subramoney

IPC: G06F9/38 ,  G06F9/30

Abstract: In one embodiment, an apparatus includes a context-based prediction circuit to receive an instruction address for a branch instruction and a plurality of predictions associated with the branch instruction from a global prediction circuit. The context-based prediction circuit may include: a table having a plurality of entries each to store a context prediction value for a corresponding branch instruction; and a control circuit to generate, for the branch instruction, an index value to index into the table, the control circuit to generate the index value based at least in part on at least some of the plurality of predictions associated with the branch instruction and the instruction address for the branch instruction. Other embodiments are described and claimed.

公开(公告)号：US10664281B2

公开(公告)日：2020-05-26

申请号：US16147670

申请日：2018-09-29

Applicant: Intel Corporation

Inventor： Ragavendra Natarajan ,  Niranjan Soundararajan ,  Saurabh Gupta ,  Sreenivas Subramoney

IPC: G06F9/38 ,  G06F9/30

Abstract: Methods and apparatuses relating to dynamic asymmetric scaling of branch predictor tables are described. Branch predictor circuits to perform dynamic asymmetric scaling of branch predictor tables are also described. In one embodiment, a processor includes an execution unit to execute a branch instruction; and a branch predictor to generate a prediction for the branch instruction from either of a plurality of global history prediction tables of differing history lengths and a floating global history prediction table, wherein the branch predictor is to: for each of the plurality of global history prediction tables, track a total number of unique entries that provide a correct prediction which is not available in a global history prediction table of lower history length within a monitoring period that includes execution of a plurality of instances of the branch instruction, and assign the floating global history prediction table as an extension to a global history prediction table of the plurality of global history prediction tables having a greatest total number of unique useful entries in the monitoring period.

公开(公告)号：US20200104137A1

公开(公告)日：2020-04-02

申请号：US16147670

申请日：2018-09-29

Applicant: Intel Corporation

Inventor： Ragavendra Natarajan ,  NIiranjan Soundararajan ,  Saurabh Gupta ,  Sreenivas Subramoney

IPC: G06F9/38

Abstract: Methods and apparatuses relating to dynamic asymmetric scaling of branch predictor tables are described. Branch predictor circuits to perform dynamic asymmetric scaling of branch predictor tables are also described. In one embodiment, a processor includes an execution unit to execute a branch instruction; and a branch predictor to generate a prediction for the branch instruction from either of a plurality of global history prediction tables of differing history lengths and a floating global history prediction table, wherein the branch predictor is to: for each of the plurality of global history prediction tables, track a total number of unique entries that provide a correct prediction which is not available in a global history prediction table of lower history length within a monitoring period that includes execution of a plurality of instances of the branch instruction, and assign the floating global history prediction table as an extension to a global history prediction table of the plurality of global history prediction tables having a greatest total number of unique useful entries in the monitoring period.

公开(公告)号：US09912474B2

公开(公告)日：2018-03-06

申请号：US14040026

申请日：2013-09-27

Applicant: Intel Corporation

Inventor： Saurabh Gupta ,  Vincent J. Zimmer

IPC: H04L9/32 ,  H04L9/08 ,  G06F21/78 ,  G06F1/32 ,  G06F21/80 ,  H04L9/12 ,  G06F3/06

CPC classification number: H04L9/0825 ,  G06F1/3203 ,  G06F1/3206 ,  G06F3/0601 ,  G06F21/78 ,  G06F21/80 ,  G06F21/805 ,  H04L9/12 ,  H04L9/32

Abstract: Methods and apparatus related to performance of telemetry, data gathering, and failure isolation using non-volatile memory are described. In one embodiment, a Non-Volatile Memory (NVM) controller logic stores data in a portion of an NVM device. The portion of the NVM device is determined based at least in part on a type or an identity of a sender of the data. Also, the data is encrypted in accordance with a public key provided by the sender. Other embodiments are also disclosed and claimed.

公开(公告)号：US11321089B2

公开(公告)日：2022-05-03

申请号：US16914338

申请日：2020-06-27

Applicant: Intel Corporation

Inventor： Saurabh Gupta ,  Niranjan Soundararajan ,  Ragavendra Natarajan ,  Sreenivas Subramoney

IPC: G06F9/30 ,  G06F9/38

Abstract: Methods and apparatuses relating to instruction set architecture (ISA) based and automatic load tracking hardware for opportunistic re-steer of data-dependent flaky branches are described. In one embodiment, a processor includes a pipeline circuit comprising a decoder to decode instructions into decoded instructions and an execution circuit to execute the decoded instructions, a branch predictor circuit to generate a predicted path for a branch instruction, and a branch re-steer circuit to, for the branch instruction dependent on a result from a load instruction, check if an instruction received by the pipeline circuit is the load instruction, and when the instruction received by the pipeline circuit is the load instruction, check for a write back of the result from the load instruction between a decode of the branch instruction with the decoder and an execution of the branch instruction with the execution circuit, and when the predicted path differs from a path based on the result from the load instruction, re-steer the branch instruction in the pipeline circuit to the path and cause execution of the branch instruction for the path based on the result from the load instruction.

公开(公告)号：US10430198B2

公开(公告)日：2019-10-01

申请号：US15870595

申请日：2018-01-12

Applicant: Intel Corporation

Inventor： Saurabh Gupta ,  Rahul Pal ,  Niranjan Soundararajan ,  Ragavendra Natarajan ,  Sreenivas Subramoney

IPC: G06F9/38

Abstract: One embodiment provides an apparatus. The apparatus includes a store direct dependent (SDD) branch prediction circuitry and an SDD management circuitry. The store direct dependent (SDD) branch prediction circuitry is to store an SDD branch table. The SDD branch table is to store at least one record. Each record includes a branch instruction pointer (IP) field, a load IP field, a store IP field, a comparison info field and at least one of a store value field and/or a predicted outcome field. The SDD management circuitry is to populate the SDD branch table at runtime and to override a baseline branch prediction associated with an incoming branch IP with an SDD branch prediction, if the SDD branch table contains a first record populated with the incoming branch IP and at least one of a store value and/or an SDD predicted outcome.

公开(公告)号：US09836307B2

公开(公告)日：2017-12-05

申请号：US14748656

申请日：2015-06-24

Applicant: Intel Corporation

Inventor： Saurabh Gupta ,  Vincent J. Zimmer ,  Rajesh Poornachandran

IPC: G06F9/00 ,  G06F15/177 ,  G06F9/44 ,  G06F9/50 ,  G06F21/57 ,  G06F21/44

CPC classification number: G06F9/4403 ,  G06F9/4401 ,  G06F9/5011 ,  G06F21/44 ,  G06F21/572

Abstract: The present disclosure is directed to firmware block dispatch based on fusing. A device may determine firmware blocks to load during initialization of the device based on fuses set in a processing module in the device. A firmware module may comprise at least a nonvolatile (NV) memory including boot code and a firmware information table (FIT). During initialization the boot code may cause the processing module to read fuse information from a fuse module and to determine at least one firmware block to load based on the fuse information. For example, the fuse information may comprise a fuse string and the processing module may compare the fuse string to the FIT table, determine at least one pointer in the FIT table associated with the fuse string and load at least one firmware block based on a location (e.g., offset) in the NV memory identified by the at least one pointer.