公开(公告)号：US20180204932A1

公开(公告)日：2018-07-19

申请号：US15570965

申请日：2015-06-17

Applicant: Intel Corporation

Inventor： Rishabh MEHANDRU ,  Partick MORROW ,  Ranjith KUMAR ,  Cory E. WEBER ,  Seiyon KIM ,  Stephen M. CEA ,  Tahir GHANI

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/06 ,  H01L27/12 ,  H01L27/108

CPC classification number: H01L29/66795 ,  H01L21/8221 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0688 ,  H01L27/10826 ,  H01L27/1104 ,  H01L27/1211 ,  H01L29/78 ,  H01L29/785

Abstract: Vertical integration schemes and circuit elements architectures for area scaling of semiconductor devices are described. In an example, an inverter structure includes a semiconductor fin separated vertically into an upper region and a lower region. A first plurality of gate structures is included for controlling the upper region of the semiconductor fin. A second plurality of gate structures is included for controlling the lower region of the semiconductor fin. The second plurality of gate structures has a conductivity type opposite the conductivity type of the first plurality of gate structures.

公开(公告)号：US20240153956A1

公开(公告)日：2024-05-09

申请号：US18409519

申请日：2024-01-10

Applicant: Intel Corporation

Inventor： Seung Hoon SUNG ,  Cheng-Ying HUANG ,  Marko RADOSAVLJEVIC ,  Christopher M. NEUMANN ,  Susmita GHOSE ,  Varun MISHRA ,  Cory WEBER ,  Stephen M. CEA ,  Tahir GHANI ,  Jack T. KAVALIEROS

IPC: H01L27/12 ,  H01L21/84

CPC classification number: H01L27/1203 ,  H01L21/84

Abstract: Embodiments disclosed herein include forksheet transistor devices having a dielectric or a conductive spine. For example, an integrated circuit structure includes a dielectric spine. A first transistor device includes a first vertical stack of semiconductor channels spaced apart from a first edge of the dielectric spine. A second transistor device includes a second vertical stack of semiconductor channels spaced apart from a second edge of the dielectric spine. An N-type gate structure is on the first vertical stack of semiconductor channels, a portion of the N-type gate structure laterally between and in contact with the first edge of the dielectric spine and the first vertical stack of semiconductor channels. A P-type gate structure is on the second vertical stack of semiconductor channels, a portion of the P-type gate structure laterally between and in contact with the second edge of the dielectric spine and the second vertical stack of semiconductor channels.

公开(公告)号：US20230095007A1

公开(公告)日：2023-03-30

申请号：US17485173

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Rishabh MEHANDRU ,  Stephen M. CEA ,  Aaron D. LILAK ,  Cory WEBER ,  Patrick KEYS ,  Navid PAYDAVOSI

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/786

Abstract: Integrated circuit structures having metal-containing source or drain structures, and methods of fabricating integrated circuit structures having metal-containing source or drain structures, are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires, and a second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal nanowires. The first and second epitaxial source or drain structures include a metal species diffused therein, the metal species further diffused partially into the vertical arrangement of horizontal nanowires.

公开(公告)号：US20220246759A1

公开(公告)日：2022-08-04

申请号：US17722142

申请日：2022-04-15

Applicant: Intel Corporation

Inventor： Rishabh MEHANDRU ,  Stephen M. CEA ,  Biswajeet GUHA ,  Tahir GHANI ,  William HSU

IPC: H01L29/78 ,  H01L21/761 ,  H01L21/762 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66

Abstract: Isolation schemes for gate-all-around (GAA) transistor devices are provided herein Integrated circuit structures including increased transistor source/drain contact area using a sacrificial source/drain layer are provided herein. In some cases, the isolation schemes include changing the semiconductor nanowires/nanoribbons in a targeted channel region between active or functional transistor devices to electrically isolate those active devices. The targeted channel region is referred to herein as a dummy channel region, as it is not used as an actual channel region for an active or functional transistor device. The semiconductor nanowires/nanoribbons in the dummy channel region can be changed by converting them to an electrical insulator and/or by adding dopant that is opposite in type relative to surrounding source/drain material (to create a p-n junction). The isolation schemes described herein enable neighboring active devices to retain strain in the nanowires/nanoribbons of their channel regions, thereby improving device performance.

公开(公告)号：US20220199771A1

公开(公告)日：2022-06-23

申请号：US17133092

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Siddharth CHOUKSEY ,  Jack T. KAVALIEROS ,  Stephen M. CEA ,  Ashish AGRAWAL ,  Willy RACHMADY

IPC: H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L27/088

Abstract: Neighboring gate-all-around integrated circuit structures having a conductive contact stressor between epitaxial source or drain regions are described. In an example, a first vertical arrangement of nanowires and a second vertical arrangement of nanowires above a substrate. A first gate stack is over the first vertical arrangement of nanowires. A second gate stack is over the second vertical arrangement of nanowires. First epitaxial source or drain structures are at ends of the first vertical arrangement of nanowires. Second epitaxial source or drain structures are at ends of the second vertical arrangement of nanowires. An intervening conductive contact structure is between neighboring ones of the first epitaxial source or drain structures and of the second epitaxial source or drain structures. The intervening conductive contact structure imparts a stress to the neighboring ones of the first epitaxial source or drain structures and of the second epitaxial source or drain structures.

公开(公告)号：US20190172950A1

公开(公告)日：2019-06-06

申请号：US16323661

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Aaron D. LILAK ,  Sean T. MA ,  Rishabh MEHANDRU ,  Patrick MORROW ,  Stephen M. CEA

IPC: H01L29/78 ,  H01L27/092 ,  H01L29/06 ,  H01L21/8238 ,  H01L21/762 ,  H01L29/66

Abstract: An integrated circuit apparatus including a body; a transistor formed on a first portion of the body, the transistor including a gate stack and a channel defined in the body between a source and a drain; and a plug formed in a second portion of the body, the plug including a material operable to impart a stress on the first portion of the body. A method of forming an integrated circuit device including forming a transistor body on a substrate; forming a transistor device in a first portion of the transistor body on a first side of the substrate; and dividing the transistor body into at least the first portion and a second portion with a plug in the transistor body, the plug including a material operable to impart a stress on the first portion of the body, wherein the material is introduced through a second side of the substrate.

公开(公告)号：US20180248005A1

公开(公告)日：2018-08-30

申请号：US15774952

申请日：2015-12-23

Applicant: Intel Corporation

Inventor： Aaron D. LILAK ,  Stephen M. CEA ,  Rishabh MEHANDRU ,  Cory E. WEBER

IPC: H01L29/10 ,  H01L29/167 ,  H01L29/78 ,  H01L21/304 ,  H01L21/306 ,  H01L21/265 ,  H01L21/324 ,  H01L29/66

CPC classification number: H01L29/1083 ,  H01L21/26513 ,  H01L21/26566 ,  H01L21/304 ,  H01L21/30625 ,  H01L21/324 ,  H01L29/167 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: Methods for doping a sub-fin region of a semiconductor structure include providing a semiconductor structure that comprises a substrate and a plurality of fins formed on the substrate, the plurality of fins having sub-fin regions adjacent to the substrate; removing the substrate to expose a portion of the sub-fin regions of the plurality of fins, and implanting a dopant material into the exposed portion of the sub-fin region. The method may also include performing an annealing process after the implantation such that the dopant becomes electrically active. The method may also include patterning the backside of the semiconductor structure. Devices constructed using the disclosed methods are also provided, and other embodiments are discussed.

公开(公告)号：US20180204955A1

公开(公告)日：2018-07-19

申请号：US15743575

申请日：2015-09-10

Applicant: Intel Corporation

Inventor： Rishabh MEHANDRU ,  Szuya S. LIAO ,  Stephen M. CEA

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L27/092 ,  H01L29/66 ,  H01L21/8238

CPC classification number: H01L29/78696 ,  B82Y10/00 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66469 ,  H01L29/66545 ,  H01L29/775

Abstract: Semiconductor nanowire devices having cavity spacers and methods of fabricating cavity spacers for semiconductor nanowire devices are described. For example, a semiconductor device includes a plurality of vertically stacked nanowires disposed above a substrate, each of the nanowires including a discrete channel region. A common gate electrode stack surrounds each of the discrete channel regions of the plurality of vertically stacked nanowires. A pair of dielectric spacers is on either side of the common gate electrode stack, each of the pair of dielectric spacers including a continuous material disposed along a sidewall of the common gate electrode and surrounding a discrete portion of each of the vertically stacked nanowires. A pair of source and drain regions is on either side of the pair of dielectric spacers.

公开(公告)号：US20170162676A1

公开(公告)日：2017-06-08

申请号：US15434981

申请日：2017-02-16

Applicant: Intel Corporation

Inventor： Annalisa CAPPELLANI ,  Stephen M. CEA ,  Tahir GHANI ,  Harry GOMEZ ,  Jack T. KAVALIEROS ,  Patrick H. KEYS ,  Seiyon KIM ,  Kelin J. KUHN ,  Aaron D. LILAK ,  Rafael RIOS ,  Mayank SAHNI

IPC: H01L29/66 ,  H01L21/762 ,  H01L29/423 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L29/66818 ,  B82Y10/00 ,  H01L21/762 ,  H01L21/76216 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785

Abstract: Semiconductor devices with isolated body portions are described. For example, a semiconductor structure includes a semiconductor body disposed above a semiconductor substrate. The semiconductor body includes a channel region and a pair of source and drain regions on either side of the channel region. An isolation pedestal is disposed between the semiconductor body and the semiconductor substrate. A gate electrode stack at least partially surrounds a portion of the channel region of the semiconductor body.

公开(公告)号：US20230046755A1

公开(公告)日：2023-02-16

申请号：US17978038

申请日：2022-10-31

Applicant: Intel Corporation

Inventor： Rishabh MEHANDRU ,  Patrick MORROW ,  Ranjith KUMAR ,  Cory E. WEBER ,  Seiyon KIM ,  Stephen M. CEA ,  Tahir GHANI

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/06 ,  H01L27/11 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/108 ,  H01L27/12

Abstract: Vertical integration schemes and circuit elements architectures for area scaling of semiconductor devices are described. In an example, an inverter structure includes a semiconductor fin separated vertically into an upper region and a lower region. A first plurality of gate structures is included for controlling the upper region of the semiconductor fin. A second plurality of gate structures is included for controlling the lower region of the semiconductor fin. The second plurality of gate structures has a conductivity type opposite the conductivity type of the first plurality of gate structures.