公开(公告)号：US20250133821A1

公开(公告)日：2025-04-24

申请号：US19000039

申请日：2024-12-23

Applicant: Intel Corporation

Inventor： Tahir GHANI ,  Mohit K. HARAN ,  Mohammad HASAN ,  Biswajeet GUHA ,  Alison V. DAVIS ,  Leonard P. GULER

IPC: H10D84/85 ,  H10D30/01 ,  H10D30/62 ,  H10D62/10

Abstract: Integrated circuit structures having cut metal gates, and methods of fabricating integrated circuit structures having cut metal gates, are described. For example, an integrated circuit structure includes a fin having a portion protruding above a shallow trench isolation (STI) structure. A gate dielectric material layer is over the protruding portion of the fin and over the STI structure. A conductive gate layer is over the gate dielectric material layer. A conductive gate fill material is over the conductive gate layer. A dielectric gate plug is laterally spaced apart from the fin, the dielectric gate plug on but not through the STI structure. The gate dielectric material layer and the conductive gate layer are not along sides of the dielectric gate plug, and the conductive gate fill material is in contact with the sides of the dielectric gate plug.

公开(公告)号：US20240355903A1

公开(公告)日：2024-10-24

申请号：US18763777

申请日：2024-07-03

Applicant: Intel Corporation

Inventor： Biswajeet GUHA ,  Dax M. CRUM ,  Stephen M. CEA ,  Leonard P. GULER ,  Tahir GHANI

IPC: H01L29/66 ,  H01L21/28 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/12 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/6653 ,  H01L21/28114 ,  H01L21/28123 ,  H01L21/76224 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/4238 ,  H01L29/66545 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/78654 ,  H01L29/78696 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/7853

Abstract: Self-aligned gate endcap (SAGE) architectures with gate-all-around devices above insulator substrates, and methods of fabricating self-aligned gate endcap (SAGE) architectures with gate-all-around devices above insulator substrates, are described. In an example, an integrated circuit structure includes includes a semiconductor nanowire above an insulator substrate and having a length in a first direction. A gate structure is around the semiconductor nanowire, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. A pair of gate endcap isolation structures is included. The first of the pair of gate endcap isolation structures is directly adjacent to the first end of the gate structure, and the second of the pair of gate endcap isolation structures is directly adjacent to the second end of the gate structure.

公开(公告)号：US20240145471A1

公开(公告)日：2024-05-02

申请号：US18408223

申请日：2024-01-09

Applicant: Intel Corporation

Inventor： Biswajeet GUHA ,  William HSU ,  Chung-Hsun LIN ,  Kinyip PHOA ,  Oleg GOLONZKA ,  Tahir GHANI ,  Kalyan KOLLURU ,  Nathan JACK ,  Nicholas THOMSON ,  Ayan KAR ,  Benjamin ORR

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/785

Abstract: Gate-all-around structures having devices with source/drain-to-substrate electrical contact are described. An integrated circuit structure includes a first vertical arrangement of horizontal nanowires above a first fin. A first gate stack is over the first vertical arrangement of horizontal nanowires. A first pair of epitaxial source or drain structures is at first and second ends of the first vertical arrangement of horizontal nanowires. One or both of the first pair of epitaxial source or drain structures is directly electrically coupled to the first fin. A second vertical arrangement of horizontal nanowires is above a second fin. A second gate stack is over the second vertical arrangement of horizontal nanowires. A second pair of epitaxial source or drain structures is at first and second ends of the second vertical arrangement of horizontal nanowires. Both of the second pair of epitaxial source or drain structures is electrically isolated from the second fin.

公开(公告)号：US20220415925A1

公开(公告)日：2022-12-29

申请号：US17358329

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Nicholas THOMSON ,  Kalyan KOLLURU ,  Ayan KAR ,  Rui MA ,  Benjamin ORR ,  Nathan JACK ,  Biswajeet GUHA ,  Brian GREENE ,  Lin HU ,  Chung-Hsun LIN

IPC: H01L27/12 ,  H01L27/02

Abstract: Substrate-less lateral diode integrated circuit structures, and methods of fabricating substrate-less lateral diode integrated circuit structures, are described. For example, a substrate-less integrated circuit structure includes a fin or a stack of nanowires. A plurality of P-type epitaxial structures is over the fin or stack of nanowires. A plurality of N-type epitaxial structures is over the fin or stack of nanowires. One or more spacings are in locations over the fin or stack of nanowires, a corresponding one of the one or more spacings extending between neighboring ones of the plurality of P-type epitaxial structures and the plurality of N-type epitaxial structures.

公开(公告)号：US20220415780A1

公开(公告)日：2022-12-29

申请号：US17356056

申请日：2021-06-23

Applicant: Intel Corporation

Inventor： William HSU ,  Biswajeet GUHA ,  Mohit K. HARAN ,  Vadym KAPINUS ,  Robert BIGWOOD ,  Nidhi KHANDELWAL ,  Henning HAFFNER ,  Kevin FISCHER

IPC: H01L23/528 ,  H01L27/088 ,  H01L21/033 ,  H01L21/8234

Abstract: Dummy gate patterning lines, and integrated circuit structures resulting therefrom, are described. For example, an integrated circuit structure includes a first gate line along a first direction. A second gate line is parallel with the first gate line along the first direction. A third gate line extends between and is continuous with the first gate line and the second gate line along a second direction, the second direction orthogonal to the first direction.

公开(公告)号：US20220336634A1

公开(公告)日：2022-10-20

申请号：US17853320

申请日：2022-06-29

Applicant: Intel Corporation

Inventor： Karthik JAMBUNATHAN ,  Biswajeet GUHA ,  Anand S. MURTHY ,  Tahir GHANI

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786 ,  H01L29/775

Abstract: Embodiments herein describe techniques, systems, and method for a semiconductor device. A nanowire transistor may include a channel region including a nanowire above a substrate, a source electrode coupled to a first end of the nanowire through a first etch stop layer, and a drain electrode coupled to a second end of the nanowire through a second etch stop layer. A gate electrode may be above the substrate to control conductivity in at least a portion of the channel region. A first spacer may be above the substrate between the gate electrode and the source electrode, and a second spacer may be above the substrate between the gate electrode and the drain electrode. A gate dielectric layer may be between the channel region and the gate electrode. Other embodiments may be described and/or claimed.

公开(公告)号：US20210305436A1

公开(公告)日：2021-09-30

申请号：US16830112

申请日：2020-03-25

Applicant: Intel Corporation

Inventor： Ayan KAR ,  Saurabh MORARKA ,  Carlos NIEVA-LOZANO ,  Kalyan KOLLURU ,  Biswajeet GUHA ,  Chung-Hsun LIN ,  Brian GREENE ,  Tahir GHANI

IPC: H01L29/93 ,  H01L29/06 ,  H01L21/02 ,  H01L29/66

Abstract: Gate-all-around integrated circuit structures including varactors are described. For example, an integrated circuit structure includes a varactor structure on a semiconductor substrate. The varactor structure includes a plurality of discrete vertical arrangements of horizontal nanowires. A plurality of gate stacks is over and surrounding corresponding ones of the plurality of discrete vertical arrangements of horizontal nanowires. The integrated circuit structure also includes a tap structure adjacent to the varactor structure on the semiconductor substrate. The tap structure includes a plurality of merged vertical arrangements of horizontal nanowires. A plurality of semiconductor structures is over and surrounding corresponding ones of the plurality of merged vertical arrangements of horizontal nanowires.

公开(公告)号：US20210249411A1

公开(公告)日：2021-08-12

申请号：US17242021

申请日：2021-04-27

Applicant: Intel Corporation

Inventor： Szuya S. LIAO ,  Biswajeet GUHA ,  Tahir GHANI ,  Christopher N. KENYON ,  Leonard P. GULER

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/66 ,  H01L21/768 ,  H01L23/535

Abstract: Self-aligned gate edge trigate and finFET devices and methods of fabricating self-aligned gate edge trigate and finFET devices are described. In an example, a semiconductor structure includes a plurality of semiconductor fins disposed above a substrate and protruding through an uppermost surface of a trench isolation region. A gate structure is disposed over the plurality of semiconductor fins. The gate structure defines a channel region in each of the plurality of semiconductor fins. Source and drain regions are on opposing ends of the channel regions of each of the plurality of semiconductor fins, at opposing sides of the gate structure. The semiconductor structure also includes a plurality of gate edge isolation structures. Individual ones of the plurality of gate edge isolation structures alternate with individual ones of the plurality of semiconductor fins.

公开(公告)号：US20200091145A1

公开(公告)日：2020-03-19

申请号：US16134824

申请日：2018-09-18

Applicant: Intel Corporation

Inventor： Biswajeet GUHA ,  Jun Sung KANG ,  Bruce BEATTIE ,  Stephen M. CEA ,  Tahir GHANI

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L21/8234

Abstract: Gate-all-around integrated circuit structures having self-aligned source or drain undercut for varied widths are described. In an example, a structure includes first and second vertical arrangements of nanowires above a substrate, the nanowires of the second vertical arrangement of nanowires having a horizontal width greater than a horizontal width of the nanowires of the first vertical arrangement of nanowires. First and second gate stack portions are over the first and second vertical arrangements of nanowires, respectively. First embedded epitaxial source or drain regions are at ends of the first vertical arrangement of nanowires and extend beneath dielectric sidewalls spacers of the first gate stack portion by a first distance. Second embedded epitaxial source or drain regions are at ends of the second vertical arrangement of nanowires and extend beneath the dielectric sidewalls spacers of the second gate stack portion by a second distance substantially the same as the first distance.

公开(公告)号：US20190139957A1

公开(公告)日：2019-05-09

申请号：US16098084

申请日：2016-07-01

Applicant: Intel Corporation

Inventor： Szuya S. LIAO ,  Biswajeet GUHA ,  Tahir GHANI ,  Christopher N. KENYON ,  Leonard P. GULER

IPC: H01L27/092 ,  H01L29/78 ,  H01L21/8238 ,  H01L21/768 ,  H01L23/535

Abstract: Self-aligned gate edge trigate and finFET devices and methods of fabricating self-aligned gate edge trigate and finFET devices are described. In an example, a semiconductor structure includes a plurality of semiconductor fins disposed above a substrate and protruding through an uppermost surface of a trench isolation region. A gate structure is disposed over the plurality of semiconductor fins. The gate structure defines a channel region in each of the plurality of semiconductor fins. Source and drain regions are on opposing ends of the channel regions of each of the plurality of semiconductor fins, at opposing sides of the gate structure. The semiconductor structure also includes a plurality of gate edge isolation structures. Individual ones of the plurality of gate edge isolation structures alternate with individual ones of the plurality of semiconductor fins.