公开(公告)号：US20180188976A1

公开(公告)日：2018-07-05

申请号：US15395615

申请日：2016-12-30

Applicant: Intel Corporation

Inventor： Gunjae Koo ,  Vivek Kozhikkottu ,  Shankar Ganesh Ramasubramanian ,  Christopher B. Wilkerson

IPC: G06F3/06 ,  G06F12/06

CPC classification number: G06F12/06 ,  G06F12/0215 ,  G06F13/16 ,  G06F13/1642 ,  G06F2212/1016 ,  G06F2212/1041

Abstract: Devices, systems, and methods for increasing the size of a read pending queue (RPQ) in a memory controller are described. An example of increasing the RPQ size can include receiving, at a memory controller, a read request for data in a memory having a physical address identification (ID) including row and column ID, performing a lookup of the RPQ for an entry having a pending read transaction with a physical address ID having the same row ID as the incoming read request, and, if the RPQ lookup returns a hit, appending the incoming read request's column ID to the physical address ID of the pending read transaction to form an appended read transaction. The appending read transaction can then be queued and processed sequentially, while occupying a single RPQ entry.

公开(公告)号：US10884853B2

公开(公告)日：2021-01-05

申请号：US16249631

申请日：2019-01-16

Applicant: Intel Corporation

Inventor： Wei Wu ,  Dinesh Somasekhar ,  Jon Stephan ,  Aravinda K. Radhakrishnan ,  Vivek Kozhikkottu

IPC: G06F11/00 ,  G06F11/10 ,  G11C29/52

Abstract: An apparatus includes a binary content addressable memory (BCAM) to store a plurality of error protection code (ECC) generated codewords (CWs), the BCAM divided into segments (sub-BCAMs), wherein the sub-BCAMs are to respectively store pre-defined first portions of the CWs, and to store corresponding second portions of a search word. In embodiments, the apparatus further includes logic circuitry, to obtain partial match results between the first portions of the CWs and corresponding second portions of the search word, and identify one or more CWs of the plurality of CWs that match the search word, based at least in part on the partial match results, wherein the match indicates that data included in the one or more CW is the same as the data included in the search word.

公开(公告)号：US20200310979A1

公开(公告)日：2020-10-01

申请号：US16367592

申请日：2019-03-28

Applicant: Intel Corporation

Inventor： Vivek Kozhikkottu ,  Esha Choukse ,  Shankar Ganesh Ramasubramanian ,  Melin Dadual ,  Suresh Chittor

IPC: G06F12/1009 ,  G06F12/0873 ,  G06F16/907 ,  G06F9/54

Abstract: In one embodiment, an apparatus includes: a page table circuit to receive a virtual address and to generate at least a portion of a physical address therefrom; and a mapping rule table coupled to the page table circuit, the mapping rule table to receive mapping metadata of a page of a system memory and, based on the mapping metadata, output a mapping rule for the page. Other embodiments are described and claimed.

公开(公告)号：US20200210284A1

公开(公告)日：2020-07-02

申请号：US16236151

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： Dinesh Somasekhar ,  Wei Wu ,  Shankar Ganesh Ramasubramanian ,  Vivek Kozhikkottu ,  Melin Dadual

IPC: G06F11/10 ,  G11C29/52 ,  H03M13/29

Abstract: Systems and methods related to data encoders that can perform error detection or correction. The encoders and decoders may minimize the addition of errors due to aliasing in error correction codes by implementing operators associated with reduced aliasing parity generating or reduced aliasing error checking matrices.

公开(公告)号：US20190146873A1

公开(公告)日：2019-05-16

申请号：US16249631

申请日：2019-01-16

Applicant: Intel Corporation

Inventor： Wei Wu ,  Dinesh Somasekhar ,  Jon Stephan ,  Aravinda K. Radhakrishnan ,  Vivek Kozhikkottu

IPC: G06F11/10 ,  G11C29/52

Abstract: An apparatus includes a binary content addressable memory (BCAM) to store a plurality of error protection code (ECC) generated codewords (CWs), the BCAM divided into segments (sub-BCAMs), wherein the sub-BCAMs are to respectively store pre-defined first portions of the CWs, and to store corresponding second portions of a search word. In embodiments, the apparatus further includes logic circuitry, to obtain partial match results between the first portions of the CWs and corresponding second portions of the search word, and identify one or more CWs of the plurality of CWs that match the search word, based at least in part on the partial match results, wherein the match indicates that data included in the one or more CW is the same as the data included in the search word.

公开(公告)号：US10268585B2

公开(公告)日：2019-04-23

申请号：US15195887

申请日：2016-06-28

Applicant: Intel Corporation

Inventor： Ashish Ranjan ,  Vivek Kozhikkottu

IPC: G06F12/08 ,  G06F12/0862 ,  G06F12/0842 ,  G06F12/0866

Abstract: An apparatus having a memory controller is described. The memory controller includes prefetch circuitry to prefetch, from a memory, data having a same row address in response to the memory controller's servicing of its request stream being stalled because of a timing constraint that prevents a change in row address. The memory controller also includes a cache to cache the prefetched data. The memory controller also includes circuitry to compare addresses of read requests in the memory controller's request stream against respective addresses of the prefetched data in the cache and to service those of the requests in the memory controller's request stream having a matching address with corresponding ones of the prefetched data in the cache.

公开(公告)号：US20180285304A1

公开(公告)日：2018-10-04

申请号：US15475571

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： Vivek Kozhikkottu ,  Shankar Ganesh Ramasubramanian ,  Kon-Woo Kwon ,  Dinesh Somasekhar

IPC: G06F13/42 ,  G06F13/36 ,  G06F13/40

Abstract: In accordance with embodiments disclosed herein, there is provided systems and methods for low latency statistical data bus inversion (DBI) for energy reduction. A transmitting component includes a transmitter and a statistical DBI circuit. The statistical DBI circuit is to receive current data to be transmitted on a data bus and is to store previous data transmitted on the data bus. The statistical DBI circuit includes inverting logic to invert bits of the current data before transmission in response to a control signal. The statistical DBI circuit includes adjacent pattern prediction logic to receive a difference vector including a comparison of the previous data and the current data, determine whether the difference vector includes a pattern predicting transmission of the current data with toggle is more efficient than without toggle, and output the control signal in the first state indicating the pattern was detected.

公开(公告)号：US20180285252A1

公开(公告)日：2018-10-04

申请号：US15477072

申请日：2017-04-01

Applicant: Intel Corporation

Inventor： Kon-Woo Kwon ,  Vivek Kozhikkottu ,  Sang Phill Park ,  Ankit More ,  William P. Griffin ,  Robert Pawlowski ,  Jason M. Howard ,  Joshua B. Fryman

IPC: G06F12/02 ,  G06F12/0802 ,  G06F12/0846 ,  G11C7/10 ,  G06F12/06

Abstract: Optimized memory access bandwidth devices, systems, and methods for processing low spatial locality data are disclosed and described. A system memory is divided into a plurality of memory subsections, where each memory subsection is communicatively coupled to an independent memory channel to a memory controller. Memory access requests from a processor are thereby sent by the memory controller to only the appropriate memory subsection.