公开(公告)号：US20200310979A1

公开(公告)日：2020-10-01

申请号：US16367592

申请日：2019-03-28

Applicant: Intel Corporation

Inventor： Vivek Kozhikkottu ,  Esha Choukse ,  Shankar Ganesh Ramasubramanian ,  Melin Dadual ,  Suresh Chittor

IPC: G06F12/1009 ,  G06F12/0873 ,  G06F16/907 ,  G06F9/54

Abstract: In one embodiment, an apparatus includes: a page table circuit to receive a virtual address and to generate at least a portion of a physical address therefrom; and a mapping rule table coupled to the page table circuit, the mapping rule table to receive mapping metadata of a page of a system memory and, based on the mapping metadata, output a mapping rule for the page. Other embodiments are described and claimed.

公开(公告)号：US11216386B2

公开(公告)日：2022-01-04

申请号：US16584612

申请日：2019-09-26

Applicant: Intel Corporation

Inventor： Vivek Kozhikkottu ,  Suresh Chittor ,  Esha Choukse ,  Shankar Ganesh Ramasubramanian

IPC: G06F12/10 ,  G06F12/1045 ,  G06F12/06 ,  G06F11/30 ,  G06F13/16 ,  G06F12/02

Abstract: Techniques for setting a 2-level auto-close timer to access a memory device include examples of setting first and second time values for the 2-level auto-close timer to cause accessed rows to auto-close following a cache line access to a row of a bank of memory devices. For these examples, the cache line access is responsive to a multi-channel address interleaving policy that causes either successive or non-successive cache line accesses to the bank of memory devices.

公开(公告)号：US11250902B2

公开(公告)日：2022-02-15

申请号：US16584724

申请日：2019-09-26

Applicant: Intel Corporation

Inventor： Douglas Heymann ,  Wei P. Chen ,  Suresh Chittor ,  George Vergis

IPC: G11C11/40 ,  G06F13/16 ,  G11C11/406 ,  G01K13/00

Abstract: Power consumption for refresh of memory devices on a memory module is reduced by each memory device on the memory module to one of a plurality of sub channels on the memory module. Each sub channel has a thermal sensor that monitors the temperature of the DRAM chips in the region. The refresh rate is increased only for the memory devices in the sub channel in which the memory devices operate above a predefined high temperature. This results in a reduction in power required by the memory module for refresh and an increase in the maximum bandwidth of the memory module.

公开(公告)号：US20190065415A1

公开(公告)日：2019-02-28

申请号：US15916394

申请日：2018-03-09

Applicant: Intel Corporation

Inventor： Murugasamy K. Nachimuthu ,  Mohan J. Kumar ,  Mohamed Arafa ,  Suresh Chittor ,  Debendra Das Sharma ,  Pankaj Kumar

IPC: G06F13/16 ,  G06F3/06 ,  G06F13/42 ,  G06F12/0802

Abstract: Technologies for providing local disaggregation of memory include a compute sled. The compute sled includes a compute engine having a processor. The compute engine receives a request to perform a memory access operation on data residing in a first memory (e.g., a storage class memory) of the compute sled. The compute engine determines whether the data is cached in a second memory (e.g., a dynamic random-access memory (DRAM)). The compute engine performs, in response to a determination that the data is not cached in the second memory via a transactional protocol over a serial link connecting the processor and the first memory, the requested memory access operation.

公开(公告)号：US10936507B2

公开(公告)日：2021-03-02

申请号：US16367592

申请日：2019-03-28

Applicant: Intel Corporation

Inventor： Vivek Kozhikkottu ,  Esha Choukse ,  Shankar Ganesh Ramasubramanian ,  Melin Dadual ,  Suresh Chittor

IPC: G06F12/10 ,  G06F12/1009 ,  G06F16/907 ,  G06F9/54 ,  G06F12/0873 ,  G06F9/4401

Abstract: In one embodiment, an apparatus includes: a page table circuit to receive a virtual address and to generate at least a portion of a physical address therefrom; and a mapping rule table coupled to the page table circuit, the mapping rule table to receive mapping metadata of a page of a system memory and, based on the mapping metadata, output a mapping rule for the page. Other embodiments are described and claimed.