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    Two-level main memory hierarchy management
    1.
    发明授权
    Two-level main memory hierarchy management 有权

    公开(公告)号：US12271305B2

    公开(公告)日：2025-04-08

    申请号：US17214818

    申请日：2021-03-27

    Applicant: Intel Corporation

    Inventor： Sai Prashanth Muralidhara ,  Alaa R. Alameldeen ,  Rajat Agarwal ,  Wei P. Chen ,  Vivek Kozhikkottu

    IPC: G06F12/0802 ,  G06F3/06

    Abstract: A two-level main memory in which both volatile memory and persistent memory are exposed to the operating system in a flat manner and data movement and management is performed in cache line granularity is provided. The operating system can allocate pages in the two-level main memory randomly across the first level main memory and the second level main memory in a memory-type agnostic manner, or, in a more intelligent manner by allocating predicted hot pages in first level main memory and predicted cold pages in second level main memory. The cache line granularity movement is performed in a “swap” manner, that is, a hot cache line in the second level main memory is swapped with a cold cache line in first level main memory because data is stored in either first level main memory or second level main memory not in both first level main memory and second level main memory.

    Memory device with local cache array
    2.
    发明授权
    Memory device with local cache array 有权

    公开(公告)号：US11144466B2

    公开(公告)日：2021-10-12

    申请号：US16433663

    申请日：2019-06-06

    Applicant: Intel Corporation

    Inventor： Jongwon Lee ,  Vivek Kozhikkottu ,  Kuljit S. Bains ,  Hussein Alameer

    IPC: G06F12/0882 ,  G11C7/10

    Abstract: An embodiment of a memory device includes technology for a memory cell array logically organized in two or more banks of at least two rows and two columns per bank, and two or more local caches respectively coupled to the two or more banks of the memory cell array, where each local cache has a size which is an integer multiple of a memory page size of the memory cell array. Other embodiments are disclosed and claimed.

    MEMORY DEVICE WITH LOCAL CACHE ARRAY
    3.
    发明申请
    MEMORY DEVICE WITH LOCAL CACHE ARRAY 审中-公开

    公开(公告)号：US20190286566A1

    公开(公告)日：2019-09-19

    申请号：US16433663

    申请日：2019-06-06

    Applicant: Intel Corporation

    Inventor： Jongwon Lee ,  Vivek Kozhikkottu ,  Kuljit S. Bains ,  Hussein Alameer

    IPC: G06F12/0882 ,  G11C7/10

    Abstract: An embodiment of a memory device includes technology for a memory cell array logically organized in two or more banks of at least two rows and two columns per bank, and two or more local caches respectively coupled to the two or more banks of the memory cell array, where each local cache has a size which is an integer multiple of a memory page size of the memory cell array. Other embodiments are disclosed and claimed.

    Low latency statistical data bus inversion for energy reduction
    5.
    发明授权
    Low latency statistical data bus inversion for energy reduction 有权

    公开(公告)号：US10853300B2

    公开(公告)日：2020-12-01

    申请号：US15475571

    申请日：2017-03-31

    Applicant: Intel Corporation

    Inventor： Vivek Kozhikkottu ,  Shankar Ganesh Ramasubramanian ,  Kon-Woo Kwon ,  Dinesh Somasekhar

    IPC: G06F13/42 ,  G06F13/36 ,  G06F13/40

    Abstract: In accordance with embodiments disclosed herein, there is provided systems and methods for low latency statistical data bus inversion (DBI) for energy reduction. A transmitting component includes a transmitter and a statistical DBI circuit. The statistical DBI circuit is to receive current data to be transmitted on a data bus and is to store previous data transmitted on the data bus. The statistical DBI circuit includes inverting logic to invert bits of the current data before transmission in response to a control signal. The statistical DBI circuit includes adjacent pattern prediction logic to receive a difference vector including a comparison of the previous data and the current data, determine whether the difference vector includes a pattern predicting transmission of the current data with toggle is more efficient than without toggle, and output the control signal in the first state indicating the pattern was detected.

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