公开(公告)号：US20190072732A1

公开(公告)日：2019-03-07

申请号：US16182450

申请日：2018-11-06

Applicant: Intel IP Corporation

Inventor： Georg Seidemann ,  Christian Geissler ,  Sven Albers ,  Thomas Wagner ,  Marc Dittes ,  Klaus Reingruber ,  Andreas Wolter ,  Richard Patten

IPC: G02B6/42 ,  G02B6/30 ,  G02B6/122 ,  G02B6/132 ,  G02B6/12

CPC classification number: G02B6/428 ,  G02B6/12002 ,  G02B6/122 ,  G02B6/1221 ,  G02B6/132 ,  G02B6/30 ,  G02B6/4232 ,  G02B6/4238 ,  G02B6/43 ,  G02B2006/12197

Abstract: Disclosed is a package comprising a substrate having a patterned surface with an optical contact area, an optical redistribution layer (oRDL) feature, and a build-up material extending over the patterned surface of the substrate and around portions of the oRDL features. In some embodiments, the package comprises a liner sheathing the oRDL features. In some embodiments, the oRDL feature extends through openings in an outer surface of the build-up material and forms posts extending outward from the outer surface. In some embodiments, the package comprises an electrical redistribution layer (eRDL) feature, at least some portion of which overlap at least some portion of the oRDL feature. In some embodiments, the package comprises an optical fiber coupled to the oRDL features.

公开(公告)号：US10209466B2

公开(公告)日：2019-02-19

申请号：US15089524

申请日：2016-04-02

Applicant: Intel IP Corporation

Inventor： Georg Seidemann ,  Christian Geissler ,  Sven Albers ,  Thomas Wagner ,  Marc Dittes ,  Klaus Reingruber ,  Andreas Wolter ,  Richard Patten

IPC: G02B6/30 ,  G02B6/42 ,  G02B6/122 ,  G02B6/132 ,  G02B6/12

Abstract: Disclosed is a package comprising a substrate having a patterned surface with an optical contact area, an optical redistribution layer (oRDL) feature, and a build-up material extending over the patterned surface of the substrate and around portions of the oRDL features. In some embodiments, the package comprises a liner sheathing the oRDL features. In some embodiments, the oRDL feature extends through openings in an outer surface of the build-up material and forms posts extending outward from the outer surface. In some embodiments, the package comprises an electrical redistribution layer (eRDL) feature, at least some portion of which overlap at least some portion of the oRDL feature. In some embodiments, the package comprises an optical fiber coupled to the oRDL features.

公开(公告)号：US20180226185A1

公开(公告)日：2018-08-09

申请号：US15862196

申请日：2018-01-04

Applicant: Intel IP Corporation

Inventor： Sven Albers ,  Klaus Reingruber ,  Andreas Wolter

IPC: H01F27/28 ,  H01F27/24

CPC classification number: H01F27/2804 ,  H01F27/06 ,  H01F27/24 ,  H01F2027/065 ,  H01F2027/2809

Abstract: An electronic package that includes a substrate; a first electronic component mounted on one side of the substrate; a second electronic component mounted on an opposing side of the substrate; a core mounted to the substrate, wherein the core extends through the substrate; a first wire electrically attached to at least one of the first electronic component and the substrate, wherein the first wire is wrapped around the core to form a first coil on the one side of the substrate; and a second wire electrically attached to at least one of the second electronic component and the substrate, wherein the second wire is wrapped around the core to form a second coil on the opposing side of the substrate.

公开(公告)号：US20180068939A1

公开(公告)日：2018-03-08

申请号：US15677835

申请日：2017-08-15

Applicant: Intel IP Corporation

Inventor： Klaus Reingruber ,  Sven Albers ,  Christian Geissler

IPC: H01L23/498 ,  H01L21/48

Abstract: Embodiments herein may relate to a package with a dielectric layer having a first face and a second face opposite the first face. A conductive line of a patterned metal redistribution layer (RDL) may be coupled with the second face of the dielectric layer. The line may include a first portion with a first width and a second portion directly coupled to the first portion, the second portion having a second width. The first portion may extend beyond a plane of the second face of the dielectric layer, and the second portion may be positioned between the first face and the second face of the dielectric layer. Other embodiments may be described and/or claimed.

公开(公告)号：US20170285280A1

公开(公告)日：2017-10-05

申请号：US15089524

申请日：2016-04-02

Applicant: Intel IP Corporation

Inventor： Georg Seidemann ,  Christian Geissler ,  Sven Albers ,  Thomas Wagner ,  Marc Dittes ,  Klaus Reingruber ,  Andreas Wolter ,  Richard Patten

IPC: G02B6/42 ,  G02B6/30 ,  G02B6/132 ,  G02B6/122

CPC classification number: G02B6/428 ,  G02B6/12002 ,  G02B6/122 ,  G02B6/1221 ,  G02B6/132 ,  G02B6/30 ,  G02B6/4232 ,  G02B6/4238 ,  G02B6/43 ,  G02B2006/12197

Abstract: Disclosed is a package comprising a substrate having a patterned surface with an optical contact area, an optical redistribution layer (oRDL) feature, and a build-up material extending over the patterned surface of the substrate and around portions of the oRDL features. In some embodiments, the package comprises a liner sheathing the oRDL features. In some embodiments, the oRDL feature extends through openings in an outer surface of the build-up material and forms posts extending outward from the outer surface. In some embodiments, the package comprises an electrical redistribution layer (eRDL) feature, at least some portion of which overlap at least some portion of the oRDL feature. In some embodiments, the package comprises an optical fiber coupled to the oRDL features.

公开(公告)号：US10741486B2

公开(公告)日：2020-08-11

申请号：US15062143

申请日：2016-03-06

Applicant: Intel IP Corporation

Inventor： Klaus Reingruber ,  Sven Albers ,  Christian Geissler

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H05K1/16 ,  H01L23/538 ,  H01L23/31 ,  H01L23/522

Abstract: Disclosed herein are electronic components having three-dimensional capacitors disposed in a metallization stack, as well as related methods and devices. In some embodiments, for example, an electronic component may include: a metallization stack and a capacitor disposed in the metallization stack wherein the capacitor includes a first conductive plate having a plurality of recesses, and a second conductive plate having a plurality of projections, wherein individual projections of the plurality of projections extend into corresponding individual recesses of the plurality of recesses without contacting the first conductive plate.

公开(公告)号：US10672731B2

公开(公告)日：2020-06-02

申请号：US15776051

申请日：2015-12-23

Applicant: Intel IP Corporation

Inventor： Sven Albers ,  Klaus Reingruber ,  Georg Seidemann ,  Christian Geissler ,  Richard Patten

IPC: H01L23/552 ,  H01L23/00 ,  H01L23/433 ,  H01L21/56 ,  H01L21/48 ,  H01L23/31 ,  H01L23/36 ,  H01L23/498

Abstract: An apparatus is described that includes a redistribution layer and a semiconductor die on the redistribution layer. An electrically conductive layer resides over the semiconductor die. A compound mold resides over the electrically conductive layer.

公开(公告)号：US20200068711A1

公开(公告)日：2020-02-27

申请号：US16343961

申请日：2016-11-23

Applicant: Intel IP Corporation

Inventor： Andreas Wolter ,  Georg Seidemann ,  Klaus Reingruber ,  Thomas Wagner

IPC: H05K1/11 ,  H05K1/18 ,  H01L23/00 ,  H05K3/34

Abstract: Systems and methods are provide to form one or more pads on at least one surface associated with a portion of a component, for example, a component associated with a surface-mounted device (SMD). Further, the systems and methods are directed to providing metal (for example, copper, Cu) layers on the surface of one or more terminations (for example, solder termination pads) of an electrical component. In one embodiment, the metal layers include metal termination pads that are fabricated on a carrier layer; components can be soldered to these termination pads, then the components with the metal pads can be debonded from the carrier layer. As such, the solder terminations of the components can be covered by the metal pads.The disclosed systems and methods can permit or otherwise facilitate a wider selection and easy availability of the components to be electrically and/or mechanically connected to semiconductor packages.

公开(公告)号：US20190121041A1

公开(公告)日：2019-04-25

申请号：US16090024

申请日：2016-03-28

Applicant: Intel IP Corporation

Inventor： Sven Albers ,  Marc Dittes ,  Andreas Wolter ,  Klaus Reingruber ,  Georg Seidemann ,  Christian Geissler ,  Thomas Wagner ,  Richard Patten

IPC: G02B6/42 ,  H01L23/00

Abstract: Embodiments of the disclosure are directed to a chip package that includes a base that includes a redistribution layer; an optical transducer circuit element on the base electrically connected to the redistribution layer; an optical element adjacent to the optical transducer circuit element and at an edge of the base; and an encasement encasing the optical transducer circuit element and a portion of the optical element, wherein one side of the optical element is exposed at an edge of the encasement and at the edge of the printed circuit board.

公开(公告)号：US10186499B2

公开(公告)日：2019-01-22

申请号：US15199434

申请日：2016-06-30

Applicant: Intel IP Corporation

Inventor： Georg Seidemann ,  Klaus Reingruber

IPC: H01L25/065 ,  H01L23/31 ,  H01L21/54 ,  H01L25/00 ,  H01L23/00 ,  H01L25/10 ,  H01L23/498 ,  H01L23/367

Abstract: IC package assemblies including a molding compound in which an IC chip surface is recessed relative to the molding compound. Thickness of the IC chip may be reduced relative to its thickness during the molding process. Another IC chip, heat spreader, etc. may then occupy the resultant recess framed by the molding compound to achieve a fine stacking pitch. In some embodiments, a package-on-package (PoP) assembly includes a center-molded IC chip flip-chip-bonded to a first package substrate. A second substrate to which a second IC chip is flip-chip bonded is then electrically coupled to the first substrate by through-molding vias. Within the PoP assembly, the second IC chip may be disposed back-to-back with the center-molded IC chip so as to occupy the recess framed by the molding compound.