公开(公告)号：US20230317833A1

公开(公告)日：2023-10-05

申请号：US18127661

申请日：2023-03-29

Applicant: Japan Display Inc.

Inventor： Hajime WATAKABE ,  Masashi TSUBUKU ,  Toshinari SASAKI ,  Takaya TAMARU

IPC: H01L29/66 ,  H01L29/786 ,  H01L29/40 ,  H01L21/385

CPC classification number: H01L29/66969 ,  H01L29/7869 ,  H01L29/401 ,  H01L21/385 ,  H01L29/78696 ,  H01L29/42384

Abstract: A method for manufacturing semiconductor device according to an embodiment includes; forming an oxide semiconductor layer above a substrate; forming a gate insulating layer above the oxide semiconductor layer; forming a metal oxide layer containing aluminum as a main component above the gate insulating layer; performing a heat treatment in a state where the metal oxide layer is formed above the gate insulating layer; removing the metal oxide layer after the heat treatment; and forming a gate electrode above the gate insulating layer.

公开(公告)号：US20230187558A1

公开(公告)日：2023-06-15

申请号：US18163045

申请日：2023-02-01

Applicant: Japan Display Inc.

Inventor： Masashi TSUBUKU ,  Michiaki SAKAMOTO ,  Takashi OKADA ,  Toshiki KANEKO ,  Tatsuya TODA

IPC: H01L29/786 ,  H01L29/417

CPC classification number: H01L29/7869 ,  H01L29/41733

Abstract: A semiconductor device includes a gate electrode on a substrate, a gate insulating film on the gate electrode, an oxide semiconductor film via the gate insulating film on the gate electrode, a source electrode and a drain electrode on the oxide semiconductor film, a protective film provided on the source electrode and the drain electrode; and a conductive layer provided on the protective film and overlapped on the oxide semiconductor layer. The protective film includes a first silicon oxide film and a first silicon nitride film. The first oxide film is in contact with the oxide semiconductor layer. The gate insulating film includes a second silicon nitride film and a second silicon oxide film. The second silicon oxide film is in contact with the oxide semiconductor layer. The oxide semiconductor layer has a first region located between the source electrode and the drain electrode in a plan view.

公开(公告)号：US20230068478A1

公开(公告)日：2023-03-02

申请号：US17894176

申请日：2022-08-24

Applicant: Japan Display Inc.

Inventor： Ryo ONODERA ,  Masashi TSUBUKU ,  Hajime WATAKABE

IPC: H01L29/786

Abstract: According to one embodiment, a semiconductor device includes a substrate, a first insulating layer disposed on the substrate, an oxide semiconductor disposed on the first insulating layer and formed in an island shape, a second insulating layer covering the oxide semiconductor, a gate electrode disposed on the second insulating layer, and a source electrode and a drain electrode in contact with the oxide semiconductor. The oxide semiconductor includes a plurality of first openings located between the gate electrode and the source electrode, and a plurality of second openings located between the gate electrode and the drain electrode, in planar view.

公开(公告)号：US20210119055A1

公开(公告)日：2021-04-22

申请号：US17036298

申请日：2020-09-29

Applicant: Japan Display Inc.

Inventor： Tatsuya TODA ,  Masashi TSUBUKU

IPC: H01L29/786 ,  H01L21/473

Abstract: A semiconductor device comprising: an oxide semiconductor layer including indium; a gate electrode facing to the oxide semiconductor layer; a gate insulating layer between the oxide semiconductor layer and the gate electrode; a first conductive layer arranged above the oxide semiconductor layer and being in contact with the oxide semiconductor layer from above the oxide semiconductor layer; an oxide portion formed on the oxide semiconductor layer and at an edge of the first conductive layer, the oxide portion being a oxide of the first conductive layer.

公开(公告)号：US20190312062A1

公开(公告)日：2019-10-10

申请号：US16368841

申请日：2019-03-28

Applicant: Japan Display Inc.

Inventor： Miyuki ISHIKAWA ,  Masashi TSUBUKU

IPC: H01L27/12 ,  H01L29/786 ,  H01L29/51 ,  H01L21/02 ,  H01L29/66 ,  H01L29/49

Abstract: One embodiment of the invention is characterized as follows. A display device comprising: a display area including a plurality of pixels, each of the pixels has a first TFT and a second TFT, the first TFT and the second TFT comprise an oxide semiconductor, the first TFT and the second TFT are covered by an interlayer insulating film, a first through hole is formed in the in the interlayer insulating film to connect a drain of the first TFT, wherein a distance d1 between a center of the first through hole and an edge of a channel of the first TFT is shorter than a distance d2 between a center of the first through hole and an edge of a channel of the second TFT, a channel length of the first TFT is shorter than a channel length of the second TFT.

公开(公告)号：US20250113618A1

公开(公告)日：2025-04-03

申请号：US18887167

申请日：2024-09-17

Applicant: Japan Display Inc.

Inventor： Hajime WATAKABE ,  Masashi TSUBUKU ,  Kentaro MIURA ,  Masahiro WATABE

IPC: H01L27/12 ,  H01L29/786

Abstract: A semiconductor device according to an embodiment of the present invention includes: a first semiconductor layer; a first gate electrode; a first gate insulating layer; a first insulating layer above the first gate electrode; a first electrode overlapping the first semiconductor layer, and electrically connected to the first semiconductor layer; a second semiconductor layer above the first insulating layer and made of a different material from the first semiconductor layer; a second gate electrode; a second gate insulating layer; a second electrode overlapping the second semiconductor layer, and electrically connected to the second semiconductor layer; and a first metal nitride layer between the second semiconductor layer and the second electrode, wherein the second semiconductor layer is polycrystalline, and an etching rate of the second semiconductor layer with respect to an etchant including phosphoric acid as a main component is less than 3 nm/min at 40° C.

公开(公告)号：US20250113543A1

公开(公告)日：2025-04-03

申请号：US18895479

申请日：2024-09-25

Applicant: Japan Display Inc.

Inventor： Hajime WATAKABE ,  Masashi TSUBUKU ,  Kentaro MIURA ,  Akihiro HANADA ,  Masahiro WATABE

IPC: H01L29/786 ,  H01L29/423

Abstract: A semiconductor device according to an embodiment of the present invention includes an oxide semiconductor layer having a polycrystalline structure and including an impurity region containing an impurity element, a gate electrode over the oxide semiconductor layer, an insulating layer between the oxide semiconductor layer and the gate electrode, a first contact hole penetrating the insulating layer and exposing the impurity region, a second contact hole penetrating at least the insulating layer and having a greater depth than the first contact hole, and a connection wiring electrically connecting the impurity region to a layer which is exposed in the second contact hole through the first contact hole and the second contact hole. The connection wiring includes a first conductive layer and a second conductive layer on the first conductive layer. A portion of the first conductive layer that is exposed from the second conductive layer contains the impurity element.

公开(公告)号：US20250015168A1

公开(公告)日：2025-01-09

申请号：US18894340

申请日：2024-09-24

Applicant: Japan Display Inc.

Inventor： Takaya TAMARU ,  Masashi TSUBUKU ,  Hajime WATAKABE ,  Toshinari SASAKI

IPC: H01L29/66 ,  G02F1/1368 ,  H01L21/02 ,  H01L29/786 ,  H10K59/121

Abstract: A method for manufacturing a semiconductor device, the method comprising steps of: forming a first metal oxide layer containing aluminium as a main component above an insulating surface; performing a planarization process on a surface of the first metal oxide layer; forming an oxide semiconductor layer on the insulating surface on which the planarization process is performed; forming a gate insulating layer above the oxide semiconductor layer; and forming a gate electrode facing the oxide semiconductor layer above the gate insulating layer.

公开(公告)号：US20240379829A1

公开(公告)日：2024-11-14

申请号：US18656855

申请日：2024-05-07

Applicant: Japan Display Inc.

Inventor： Hajime WATAKABE ,  Masashi TSUBUKU ,  Toshinari SASAKI ,  Takaya TAMARU ,  Marina MOCHIZUKI ,  Ryo ONODERA ,  Masahiro WATABE

IPC: H01L29/66 ,  G02F1/1368 ,  H01L29/45 ,  H01L29/786 ,  H10K59/122

Abstract: A semiconductor device includes a gate electrode, a gate insulating layer over the gate electrode, an oxide semiconductor layer having a polycrystalline structure over the gate insulating layer, a source electrode and a drain electrode over the oxide semiconductor layer, and an interlayer insulating layer in contact with the oxide semiconductor layer, the interlayer insulating layer covering the source electrode and the drain electrode. The oxide semiconductor layer includes a first region overlapping one of the source electrode and the drain electrode and a second region in contact with the interlayer insulating layer. A difference between a thickness of the first region and a thickness of the second region is less than or equal to 1 nm.

公开(公告)号：US20240282889A1

公开(公告)日：2024-08-22

申请号：US18647501

申请日：2024-04-26

Applicant: Japan Display Inc. ,  TOSOH CORPORATION

Inventor： Masumi NISHIMURA ,  Masashi TSUBUKU ,  Yoshihiro UEOKA ,  Yuya SUEMOTO ,  Masami MESUDA

IPC: H01L33/32 ,  H01L33/00 ,  H01L33/12 ,  H01L33/16

CPC classification number: H01L33/32 ,  H01L33/007 ,  H01L33/12 ,  H01L33/16

Abstract: A stacked structure includes an amorphous substrate, a buffer layer on the amorphous substrate, and a gallium nitride-based semiconductor layer on the buffer layer. The gallium nitride-based semiconductor layer includes at least one gallium nitride layer, and an oxygen concentration of the gallium nitride layer is less than 1×1021/cm3.