公开(公告)号：US20250015168A1

公开(公告)日：2025-01-09

申请号：US18894340

申请日：2024-09-24

Applicant: Japan Display Inc.

Inventor： Takaya TAMARU ,  Masashi TSUBUKU ,  Hajime WATAKABE ,  Toshinari SASAKI

IPC: H01L29/66 ,  G02F1/1368 ,  H01L21/02 ,  H01L29/786 ,  H10K59/121

Abstract: A method for manufacturing a semiconductor device, the method comprising steps of: forming a first metal oxide layer containing aluminium as a main component above an insulating surface; performing a planarization process on a surface of the first metal oxide layer; forming an oxide semiconductor layer on the insulating surface on which the planarization process is performed; forming a gate insulating layer above the oxide semiconductor layer; and forming a gate electrode facing the oxide semiconductor layer above the gate insulating layer.

公开(公告)号：US20240379829A1

公开(公告)日：2024-11-14

申请号：US18656855

申请日：2024-05-07

Applicant: Japan Display Inc.

Inventor： Hajime WATAKABE ,  Masashi TSUBUKU ,  Toshinari SASAKI ,  Takaya TAMARU ,  Marina MOCHIZUKI ,  Ryo ONODERA ,  Masahiro WATABE

IPC: H01L29/66 ,  G02F1/1368 ,  H01L29/45 ,  H01L29/786 ,  H10K59/122

Abstract: A semiconductor device includes a gate electrode, a gate insulating layer over the gate electrode, an oxide semiconductor layer having a polycrystalline structure over the gate insulating layer, a source electrode and a drain electrode over the oxide semiconductor layer, and an interlayer insulating layer in contact with the oxide semiconductor layer, the interlayer insulating layer covering the source electrode and the drain electrode. The oxide semiconductor layer includes a first region overlapping one of the source electrode and the drain electrode and a second region in contact with the interlayer insulating layer. A difference between a thickness of the first region and a thickness of the second region is less than or equal to 1 nm.

公开(公告)号：US20240021668A1

公开(公告)日：2024-01-18

申请号：US18335447

申请日：2023-06-15

Applicant: Japan Display Inc.

Inventor： Hajime WATAKABE ,  Masashi TSUBUKU ,  Toshinari SASAKI ,  Takaya TAMARU

IPC: H01L29/04 ,  H01L21/02

CPC classification number: H01L29/04 ,  H01L21/02595 ,  H01L21/02609 ,  H01L21/02554 ,  H01L21/02129

Abstract: A semiconductor device includes an oxide semiconductor layer having a polycrystalline structure on an insulating surface, a gate electrode over the oxide semiconductor layer, and a gate insulating layer between the oxide semiconductor layer and the gate electrode. The oxide semiconductor layer includes a first region having a first crystal structure overlapping the gate electrode and a second region having a second crystal structure not overlapping the gate electrode. An electrical conductivity of the second region is larger than an electrical conductivity of the first region. The second crystal structure is identical to the first crystal structure.

公开(公告)号：US20250113542A1

公开(公告)日：2025-04-03

申请号：US18887091

申请日：2024-09-17

Applicant: Japan Display Inc.

Inventor： Hajime WATAKABE ,  Masashi TSUBUKU ,  Kentaro MIURA ,  Akihiro HANADA ,  Takaya TAMARU ,  Masahiro WATABE

IPC: H01L29/786

Abstract: A semiconductor device comprises a first insulating layer; an oxide semiconductor layer having a polycrystalline structure on the first insulating layer; a gate insulating layer on the semiconductor oxide layer; a buffer layer on the gate insulating layer; a gate wiring on the buffer layer; and a second insulating layer on the gate wiring. The oxide semiconductor layer has a first region, a second region and a third region aligned toward a first direction. An electrical resistivity of the second region is higher than an electrical resistivity of the first region and lower than an electrical resistivity of the third region. A sheet resistance of the third region is less than 1000 ohm/square.

公开(公告)号：US20250063761A1

公开(公告)日：2025-02-20

申请号：US18934397

申请日：2024-11-01

Applicant: Japan Display Inc.

Inventor： Hajime WATAKABE ,  Masashi TSUBUKU ,  Toshinari SASAKI ,  Takaya TAMARU

IPC: H01L29/786 ,  G02F1/1368 ,  H01L29/66 ,  H10K59/121

Abstract: A semiconductor device includes a metal oxide layer containing aluminum over an insulating surface and an oxide semiconductor layer over the metal oxide layer. The oxide semiconductor layer includes a first crystal region in contact with the metal oxide layer and a second crystal region in contact with the first crystal region and having a larger area than the first crystal region in a cross-sectional view of the oxide semiconductor layer. The first crystal region and the second crystal region differ from each other in at least one of a crystal structure and a crystal orientation.

公开(公告)号：US20250022965A1

公开(公告)日：2025-01-16

申请号：US18898827

申请日：2024-09-27

Applicant: Japan Display Inc.

Inventor： Masashi TSUBUKU ,  Toshinari SASAKI ,  Hajime WATAKABE ,  Takaya TAMARU

IPC: H01L29/786 ,  H01L29/66

Abstract: A semiconductor device according to an embodiment includes: a metal oxide layer above a substrate, the metal oxide layer containing aluminum as a main component; an oxide semiconductor layer above the metal oxide layer; a gate electrode facing the oxide semiconductor layer; and a gate insulating layer between the oxide semiconductor layer and the gate electrode, wherein the oxide semiconductor layer includes two or more metals including indium, and a ratio of indium in the two or more metals is 50% or more.

公开(公告)号：US20250022964A1

公开(公告)日：2025-01-16

申请号：US18760532

申请日：2024-07-01

Applicant: Japan Display Inc.

Inventor： Hajime WATAKABE ,  Masashi TSUBUKU ,  Toshinari SASAKI ,  Takaya TAMARU ,  Marina MOCHIZUKI ,  Ryo ONODERA ,  Masahiro WATABE

IPC: H01L29/786 ,  H01L29/423

Abstract: A semiconductor device comprises a first insulating layer, an oxide semiconductor layer having a polycrystalline structure on the first insulating layer, a gate insulating layer on the oxide semiconductor layer, a gate wiring on the gate insulating layer, and a second insulating layer on the gate wiring. The oxide semiconductor layer has a first region, a second region and a third region aligned toward a first direction. The first region overlaps the gate insulating layer and the gate wiring. The third region is in contact with the second insulating layer. A distance from a top surface of the second region to a top surface of the second insulating layer is longer than a distance from a top surface of the third region to the top surface of the second insulating layer.

公开(公告)号：US20250015198A1

公开(公告)日：2025-01-09

申请号：US18894269

申请日：2024-09-24

Applicant: Japan Display Inc. ,  IDEMITSU KOSAN CO., LTD.

Inventor： Hajime WATAKABE ,  Masashi TSUBUKU ,  Toshinari SASAKI ,  Takaya TAMARU ,  Emi KAWASHIMA ,  Yuki TSURUMA ,  Daichi SASAKI

IPC: H01L29/786 ,  C01G15/00 ,  C23C14/08 ,  H01L29/66

Abstract: An oxide semiconductor film having crystallinity over a substrate contains indium (In) and a first metal element (M1). The oxide semiconductor film includes a plurality of crystal grains. Each of the plurality of crystal grains includes at least one of a crystal orientation , a crystal orientation , and a crystal orientation obtained by an electron backscatter diffraction (EBSD) method. In occupancy rates of crystal orientations calculated based on measurement points having crystal orientations with a crystal orientation difference greater than or equal to 0 degrees and less than or equal to 15 degrees with respect to a normal direction of a surface of the substrate, an occupancy rate of the crystal orientation is greater than an occupancy rate of the crystal orientation and an occupancy rate of the crystal orientation .

公开(公告)号：US20240288739A1

公开(公告)日：2024-08-29

申请号：US18433729

申请日：2024-02-06

Applicant: Japan Display Inc.

Inventor： Hajime WATAKABE ,  Masashi TSUBUKU ,  Toshinari SASAKI ,  Takaya TAMARU ,  Marina MOCHIZUKI ,  Ryo ONODERA

IPC: G02F1/1362 ,  G02F1/1368 ,  H01L27/12

CPC classification number: G02F1/136295 ,  G02F1/13685 ,  H01L27/124 ,  H01L27/1255 ,  H01L27/1274 ,  H01L27/1225

Abstract: An electronic device comprises a first stacked structure including a first oxide semiconductor layer having a polycrystalline structure, a first insulating layer on the first oxide semiconductor layer, and a first conductive layer overlapping the first oxide semiconductor layer via the first insulating layer; and a second stacked structure including a second oxide semiconductor layer composed of the same layer as the first oxide semiconductor layer, the first insulating layer on the second oxide semiconductor layer, and a second conductive layer overlapping the second oxide semiconductor layer via the first insulating layer and composed of the same layer as the first conductive layer. A portion of the first oxide semiconductor layer not overlapping the first conductive layer contains an impurity element, and the second oxide semiconductor layer does not contain the impurity element.

公开(公告)号：US20230292551A1

公开(公告)日：2023-09-14

申请号：US18176503

申请日：2023-03-01

Applicant: Japan Display Inc.

Inventor： Masashi TSUBUKU ,  Takeshi SAKAI ,  Kentaro MIURA ,  Hajime WATAKABE ,  Takaya TAMARU ,  Hiroshi TABATAKE ,  Yutaka UMEDA

IPC: H10K59/121

CPC classification number: H10K59/1213 ,  H01L27/1255

Abstract: A display device includes a light-emitting element; a first transistor and a second transistor connected in series between the light-emitting element and a driving power line; a third transistor electrically connected to a gate electrode of the first transistor; and a fourth transistor connected in parallel between a drain electrode of the first transistor and the light-emitting element, wherein a ratio of a channel width W1 to a channel length L1 of the first transistor (a W1/L1 ratio) and a ratio of a channel width W2 to a channel length L2 of the second transistor (a W2/L2 ratio) are larger than a ratio of a channel width W3 to a channel length L3 of the third transistor (a W3/L3 ratio) and a ratio of a channel width W4 to a channel length L4 of the fourth transistor (a W4/L4 ratio).