公开(公告)号：US20240168335A1

公开(公告)日：2024-05-23

申请号：US18502178

申请日：2023-11-06

Applicant: Japan Display Inc.

Inventor： Akihiro HANADA ,  Takuo KAITOH ,  Ryo ONODERA ,  Tomoyuki ITO ,  Yoshinori TANAKA

IPC: G02F1/13357 ,  G02F1/1334 ,  H01L27/12

CPC classification number: G02F1/133615 ,  G02F1/1334 ,  H01L27/1225

Abstract: A display device includes a first nitride insulating film arranged on a first substrate, a gate electrode arranged along a first direction on the first nitride insulating film, a second nitride insulating film arranged on the gate electrode, a first oxide insulating film arranged on the second nitride insulating film, and an oxide semiconductor layer arranged on the first oxide insulating film, wherein the gate electrode has a first titanium layer, an aluminum layer, and a second titanium layer stacked in order from the first nitride insulating film side, and a thickness of the second titanium layer is greater than a thickness of the first titanium layer.

公开(公告)号：US20220246764A1

公开(公告)日：2022-08-04

申请号：US17724512

申请日：2022-04-20

Applicant: Japan Display Inc.

Inventor： Isao SUZUMURA ,  Hajime WATAKABE ,  Akihiro HANADA ,  Ryo ONODERA ,  Tomoyuki ITO

IPC: H01L29/786

Abstract: The present invention addresses the problem of: realizing a TFT that uses an oxide semiconductor and that is capable of maintaining stable characteristics even in the case where the TFT is miniaturized; and realizing a display device that has high-definition pixels using such a TFT. To solve this problem, the present invention has the following configuration. A semiconductor device including an oxide semiconductor TFT formed using an oxide semiconductor film 109, the semiconductor device being characterized in that: the channel length of the oxide semiconductor TFT is 1.3 to 2.3 μm; and the sheet resistance of a source region 1092 and a drain region 1091 of the oxide semiconductor film 109 is 1.4 to 20 KΩ/□.

公开(公告)号：US20220181493A1

公开(公告)日：2022-06-09

申请号：US17542515

申请日：2021-12-06

Applicant: Japan Display Inc.

Inventor： Kentaro MIURA ,  Hajime WATAKABE ,  Ryo ONODERA

IPC: H01L29/786 ,  H01L29/66

Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes forming a first insulating layer above a polycrystalline silicon semiconductor, forming an oxide semiconductor on the first insulating layer, forming a second insulating layer on the oxide semiconductor, forming contact holes penetrating to the polycrystalline silicon semiconductor in insulating layers including the first insulating layer and the second insulating layer, forming a metal film on the second insulating layer, forming a patterned resist on the metal film, etching the metal film using the resist as a mask, performing ion implantation into the oxide semiconductor without removing the resist, and removing the resist.

公开(公告)号：US20220165826A1

公开(公告)日：2022-05-26

申请号：US17533127

申请日：2021-11-23

Applicant: Japan Display Inc.

Inventor： Akihiro HANADA ,  Kentaro MIURA ,  Hajime WATAKABE ,  Ryo ONODERA

IPC: H01L27/32 ,  H01L51/56

Abstract: According to one embodiment, in a display device, a first transistor includes a first semiconductor layer, in which a first source region includes a first region in contact a the first source electrode and a first drain region includes a second region in contact with a first drain electrode, the first source and drain regions, the first region, and the second region each include a first impurity element, and, in a region close to an interface between the first semiconductor layer and a first insulating layer, a concentration of the first impurity element included in the first and second regions is higher than a concentration of the first impurity element included in the first source region and the first drain region.

公开(公告)号：US20220140117A1

公开(公告)日：2022-05-05

申请号：US17511633

申请日：2021-10-27

Applicant: Japan Display Inc.

Inventor： Akihiro HANADA ,  Takuo KAITOH ,  Ryo ONODERA ,  Takashi OKADA ,  Tomoyuki ITO ,  Toshiki KANEKO

IPC: H01L29/66 ,  H01L29/786 ,  H01L21/385

Abstract: According to one embodiment, a method for manufacturing a semiconductor device, includes forming a first insulating film which covers a gate electrode, forming an island-shaped oxide semiconductor in contact with the first insulating film, forming a second insulating film which covers the oxide semiconductor, forming a source electrode in contact with the oxide semiconductor, forming a drain electrode in contact with the oxide semiconductor, forming a third insulating film which covers the source electrode and the drain electrode and forming a channel region between the source electrode and the drain electrode by supplying oxygen from the third insulating film to the oxide semiconductor via the second insulating film.

公开(公告)号：US20250133874A1

公开(公告)日：2025-04-24

申请号：US18989284

申请日：2024-12-20

Applicant: Japan Display Inc.

Inventor： Ryo ONODERA ,  Masumi NISHIMURA

IPC: H10H20/825 ,  H10H20/01 ,  H10H20/817 ,  H10H20/831

Abstract: A gallium nitride-based semiconductor device includes an amorphous substrate, an orientation control layer on the amorphous substrate, a gallium nitride-based semiconductor layer on the orientation control layer, and at least one electrode in contact with the gallium nitride-based semiconductor layer. The at least one electrode is formed on the gallium nitride-based semiconductor layer by vacuum evaporation using a resistance heating evaporation source as a metallic material as a vapor deposition material.

公开(公告)号：US20240332428A1

公开(公告)日：2024-10-03

申请号：US18617858

申请日：2024-03-27

Applicant: Japan Display Inc.

Inventor： Masahiro WATABE ,  Masashi TSUBUKU ,  Hajime WATAKABE ,  Toshinari SASAKI ,  Marina MOCHIZUKI ,  Takaya TAMARU ,  Ryo ONODERA

IPC: H01L29/786 ,  H01L27/12 ,  H01L29/423

CPC classification number: H01L29/7869 ,  H01L27/1248 ,  H01L29/42384

Abstract: A semiconductor device comprises a first insulating layer; a metal oxide layer mainly composed of aluminum on the first insulating layer; an oxide semiconductor layer having a polycrystalline structure on the metal oxide layer; a gate insulating layer on the oxide semiconductor layer; a gate electrode on the gate insulating layer; and a second insulating layer on the gate electrode. The metal oxide layer and the oxide semiconductor layer are both patterned, and the oxide semiconductor layer has a first region in contact with the gate insulating layer and a second region continuous with the first region in a first direction and in contact with the gate insulating layer and the second insulating layer.

公开(公告)号：US20240290861A1

公开(公告)日：2024-08-29

申请号：US18435094

申请日：2024-02-07

Applicant: Japan Display Inc.

Inventor： Hajime WATAKABE ,  Masashi TSUBUKU ,  Toshinari SASAKI ,  Takaya TAMARU ,  Marina MOCHIZUKI ,  Ryo ONODERA ,  Masahiro WATABE

IPC: H01L29/49 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/4908 ,  H01L29/66969 ,  H01L29/78648 ,  H01L29/7869

Abstract: A semiconductor device according to an embodiment includes: a first gate electrode; a first insulating layer on the first gate electrode; an oxide semiconductor layer on the first insulating layer; a second insulating layer on the oxide semiconductor layer; and a second gate electrode on the second insulating layer. The first insulating layer includes a first layer including silicon and nitrogen, a second layer including silicon and oxygen, and a third layer including aluminum and oxygen. A thickness of the first layer is 10 nm or more and 190 nm or less. A thickness of the second layer is 10 nm or more and 100 nm or less. A total thickness of the first layer and the second layer is 200 nm or less. A thickness of the third layer 1 nm or more and 10 nm or less.

公开(公告)号：US20240088192A1

公开(公告)日：2024-03-14

申请号：US18515288

申请日：2023-11-21

Applicant: Japan Display Inc.

Inventor： Hajime WATAKABE ,  Akihiro HANADA ,  Marina MOCHIZUKI ,  Ryo ONODERA ,  Fumiya KIMURA ,  Isao SUZUMURA

IPC: H01L27/146

CPC classification number: H01L27/14643 ,  H01L27/1461 ,  H01L27/14636 ,  H01L27/14689

Abstract: The present invention provides a technology which realizes a reliable semiconductor device including a photosensor device by preventing pent roofs of edges of a P+ layer from being generated and a metal wiring installed over the P+ layer from coming down while securing the electrical conductivity of the P+ layer. The semiconductor device includes a photosensor including a photodiode formed on a substrate. The photodiode includes: a cathode electrode; a laminated structure that is formed on the cathode electrode and in which an N+ layer, an I layer, and a P+ layer are laminated in this order; an anode electrode formed on the P+ layer; a first insulating film formed so as to cover a portion of the anode electrode and edges of the laminated structure; and a metal wiring connected to the anode electrode. The edges of the laminated structure are formed in forward tapered shapes in a cross-sectional view.

公开(公告)号：US20230387320A1

公开(公告)日：2023-11-30

申请号：US18447470

申请日：2023-08-10

Applicant: Japan Display Inc.

Inventor： Akihiro HANADA ,  Hajime WATAKABE ,  Ryo ONODERA

IPC: H01L29/786 ,  H01L29/36

CPC classification number: H01L29/7869 ,  H01L29/36

Abstract: A semiconductor device includes a first conductive layer, a first insulating layer on the first conductive layer, an oxide semiconductor layer on the first insulating layer, and second and third conductive layers on the oxide semiconductive layer. The oxide semiconductor layer includes a first region, a second region in contact with the second conductive layer, a third region in contact with the third conductive layer, a first impurity region between the first region and the second region, and a second impurity region between the first region and the third region. The first impurity region is in contact with the second conductive layer. The second impurity region is in contact with the third conductive layer. An electrical conductivity of each of the first impurity region and the second impurity region is greater than an electrical conductivity of each of the second region and the third region.