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    Fabricating memory devices with optimized gate oxide thickness
    11.
    发明授权
    Fabricating memory devices with optimized gate oxide thickness 有权

    公开(公告)号：US10600793B2

    公开(公告)日：2020-03-24

    申请号：US16397943

    申请日：2019-04-29

    Applicant: Marvell World Trade Ltd.

    Inventor： Runzi Chang ,  Winston Lee ,  Peter Lee

    IPC: H01L27/112 ,  G11C17/16 ,  G11C17/18 ,  H01L21/311 ,  H01L23/525 ,  H01L29/423 ,  H01L21/02 ,  H01L21/027

    Abstract: The present disclosure describes apparatuses and methods for manufacturing programmable memory devices with optimized gate oxide thickness. In some aspects, lithography masks are used to fabricate oxide gates for programmable memory devices of an integrated-circuit (IC) die that are thinner than oxide gates fabricated for processor core devices of the IC die. In other aspects, lithography masks are used to fabricate oxide gates for the programmable memory devices of the IC die such that they are thicker than the oxide gates fabricated for the processor core devices of the IC die. By so doing, the programmable memory devices can be manufactured with optimized gate oxide thickness that may reduce programming voltage or increase device reliability of the programmable memory devices.

    Method of creating aligned vias in ultra-high density integrated circuits
    12.
    发明授权
    Method of creating aligned vias in ultra-high density integrated circuits 有权

    公开(公告)号：US10522394B2

    公开(公告)日：2019-12-31

    申请号：US16106205

    申请日：2018-08-21

    Applicant: Marvell World Trade LTD.

    Inventor： Runzi Chang ,  Min She

    IPC: H01L21/768 ,  H01L21/027 ,  H01L21/033 ,  H01L21/67 ,  H01L21/02 ,  H01L21/311 ,  H01L21/288

    Abstract: A method of forming vias aligned with metal lines in an integrated circuit is provided. The method includes: forming a stacked dielectric, capped, hard mask, and first film and photoresist layers; patterning first photoresist layer to provide metal line masks; etching hard mask layer based on patterned first photoresist layer to form metal line masks; ashing first photoresist and film layers; forming second film and photoresist layers on hard mask layer; patterning second photoresist layer to form via masks across opposing sides of metal line masks; etching second film and capped layers based on patterned second photoresist layer; ashing second photoresist and film layers; etching dielectric and capped layers based on a pattern of hard mask layer to provide via and metal line regions; etching hard mask and capped layers; and performing dual damascene process operations to form vias and metal lines in via and metal line regions.

    RESISTIVE RANDOM ACCESS MEMORY AND METHOD FOR CONTROLLING MANUFACTURING OF CORRESPONDING SUB-RESOLUTION FEATURES OF CONDUCTIVE AND RESISTIVE ELEMENTS
    14.
    发明申请
    RESISTIVE RANDOM ACCESS MEMORY AND METHOD FOR CONTROLLING MANUFACTURING OF CORRESPONDING SUB-RESOLUTION FEATURES OF CONDUCTIVE AND RESISTIVE ELEMENTS 有权
    电阻随机存取存储器及其控制方法，用于控制导电和电阻元件的相关分解特征的制造

    公开(公告)号：US20140170832A1

    公开(公告)日：2014-06-19

    申请号：US14102922

    申请日：2013-12-11

    Applicant: Marvell World Trade Ltd.

    Inventor： Pantas Sutardja ,  Albert Wu ,  Runzi Chang ,  Winston Lee ,  Peter Lee

    IPC: H01L45/00 ,  H01L49/02

    CPC classification number: H01L45/04 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/1233 ,  H01L45/1675

    Abstract: A method including: forming a stack of resistive layers; prior to or subsequent to forming the stack of resistive layers, forming a conductive layer; applying a mask layer on the stack of resistive layers or the conductive layer; forming a first spacer on the mask layer; and etching away a first portion of the mask layer using the first spacer as a first mask to provide a remainder. The method further includes: forming a second spacer on the stack of the resistive layers or the conductive layer and the remainder of the mask layer; etching away a second portion of the remainder of the mask layer to form an island; and using the island as a second mask, etching the stack of the resistive layers to form a resistive element of a memory, and etching the conductive layer to form a conductive element of the memory.

    Abstract translation: 一种方法，包括：形成一层电阻层; 在形成电阻层堆叠之前或之后，形成导电层; 在电阻层或导电层的叠层上施加掩模层; 在掩模层上形成第一间隔物; 并且使用第一间隔件作为第一掩模蚀刻掉掩模层的第一部分以提供其余部分。 该方法还包括：在电阻层或导电层和掩模层的其余部分的叠层上形成第二间隔物; 蚀刻掉掩模层的其余部分的第二部分以形成岛; 并且使用岛作为第二掩模，蚀刻电阻层的堆叠以形成存储器的电阻元件，并蚀刻导电层以形成存储器的导电元件。

    ISOLATION COMPONENTS FOR TRANSISTORS FORMED ON FIN FEATURES OF SEMICONDUCTOR SUBSTRATES
    15.
    发明申请
    ISOLATION COMPONENTS FOR TRANSISTORS FORMED ON FIN FEATURES OF SEMICONDUCTOR SUBSTRATES 审中-公开
    用于晶体管的分离元件在半导体衬底的特征上形成

    公开(公告)号：US20140103452A1

    公开(公告)日：2014-04-17

    申请号：US14051299

    申请日：2013-10-10

    Applicant: Marvell World Trade Ltd.

    Inventor： Runzi Chang ,  Chuan-Cheng Cheng

    IPC: H01L27/088 ,  H01L29/66

    CPC classification number: H01L21/823431 ,  H01L21/28035 ,  H01L21/76224 ,  H01L21/764 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/66795

    Abstract: In an embodiment, an apparatus includes a substrate including a surface having a planar portion and a fin feature extending in a direction substantially perpendicular to the planar portion and having a thickness less than a thickness of the substrate. The apparatus also includes a first transistor that includes a first gate region formed over the fin feature, a first source region formed from a body of the fin feature, and a first drain region formed from the body of the fin feature. Additionally, the apparatus includes a second transistor that includes a second gate region formed over the fin feature, a second source region formed from the body of the fin feature, and a second drain region formed from the body of the fin feature. Further, the apparatus includes an isolation component formed between the first transistor and the second transistor, where the isolation component has a width less than 30 nm.

    Abstract translation: 在一个实施例中，一种装置包括基底，该基底包括具有平坦部分的表面和沿基本上垂直于该平面部分的方向延伸并且具有小于该基底的厚度的厚度的翅片特征。 该装置还包括第一晶体管，其包括形成在鳍片特征上的第一栅极区域，由鳍状物体的主体形成的第一源极区域和由鳍状物体的主体形成的第一漏极区域。 此外，该装置包括第二晶体管，其包括形成在鳍片特征上的第二栅极区域，由鳍片特征体形成的第二源极区域和由鳍片特征体形成的第二漏极区域。 此外，该装置包括形成在第一晶体管和第二晶体管之间的隔离部件，其中隔离部件具有小于30nm的宽度。

    Sub-Device Field-Effect Transistor Architecture for Integrated Circuits
    16.
    发明申请
    Sub-Device Field-Effect Transistor Architecture for Integrated Circuits 审中-公开

    公开(公告)号：US20200066706A1

    公开(公告)日：2020-02-27

    申请号：US16372905

    申请日：2019-04-02

    Applicant: Marvell World Trade Ltd.

    Inventor： Runzi Chang

    IPC: H01L27/02 ,  H01L21/8234 ,  H01L27/088 ,  H03K17/687

    Abstract: The present disclosure describes aspects of a sub-device field-effect transistor architecture for integrated circuits. In some aspects, an integrated field-effect transistor (FET) is implemented with multiple FET sub-devices. During operation, source-side FET sub-devices of the integrated FET may operate in the linear region instead of in saturation. Operating in the linear region, the source-side FET sub-devices of the integrated FET may exhibit less threshold voltage or current sensitivity than other drain-side FET sub-devices that operate in saturation. A device layout of the integrated FET may be designed such that the less sensitive source-side FET sub-devices surround or protect the other more sensitive drain-side FET sub-devices from random variations or density issues at edges of the device layout. By so doing, a threshold voltage or current sensitivity of the integrated FET may be reduced, resulting in improved matching between integrated FET devices.

    Isolation components for transistors formed on fin features of semiconductor substrates
    17.
    发明授权
    Isolation components for transistors formed on fin features of semiconductor substrates 有权

    公开(公告)号：US10217669B2

    公开(公告)日：2019-02-26

    申请号：US15211256

    申请日：2016-07-15

    Applicant: Marvell World Trade Ltd.

    Inventor： Runzi Chang ,  Chuan-Cheng Cheng

    IPC: H01L21/76 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L21/84 ,  H01L21/762 ,  H01L21/764 ,  H01L27/12 ,  H01L21/28

    Abstract: In an embodiment, a method comprises: forming a fin feature on a portion of a surface of a substrate; forming a first region of polycrystalline silicon over a first portion of the fin feature; forming a second region of polycrystalline silicon over a second portion of the fin feature; forming a third region of polycrystalline silicon over a third portion of the fin feature, wherein the third region of polycrystalline silicon is disposed between (i) the first region and (ii) the second region; forming a first spacer region between the first region and the third region; forming a second spacer region between the second region and the third region; removing the third region and at least a portion of the fin feature formed under the third region to thereby form a gap; and disposing a second dielectric material into the gap to form an isolation component.

    ISOLATION COMPONENTS FOR TRANSISTORS FORMED ON FIN FEATURES OF SEMICONDUCTOR SUBSTRATES
    20.
    发明申请
    ISOLATION COMPONENTS FOR TRANSISTORS FORMED ON FIN FEATURES OF SEMICONDUCTOR SUBSTRATES 审中-公开
    用于晶体管的分离元件在半导体衬底的特征上形成

    公开(公告)号：US20160329249A1

    公开(公告)日：2016-11-10

    申请号：US15211256

    申请日：2016-07-15

    Applicant: Marvell World Trade Ltd.

    Inventor： Runzi Chang ,  Chuan-Cheng Cheng

    IPC: H01L21/8234 ,  H01L29/66 ,  H01L21/28 ,  H01L21/762

    CPC classification number: H01L21/823431 ,  H01L21/28035 ,  H01L21/76224 ,  H01L21/764 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/66795

    Abstract: In an embodiment, a method comprises: forming a fin feature on a portion of a surface of a substrate; forming a first region of polycrystalline silicon over a first portion of the fin feature; forming a second region of polycrystalline silicon over a second portion of the fin feature; forming a third region of polycrystalline silicon over a third portion of the fin feature, wherein the third region of polycrystalline silicon is disposed between (i) the first region and (ii) the second region; forming a first spacer region between the first region and the third region; forming a second spacer region between the second region and the third region; removing the third region and at least a portion of the fin feature formed under the third region to thereby form a gap; and disposing a second dielectric material into the gap to form an isolation component.

    Abstract translation: 在一个实施例中，一种方法包括：在衬底表面的一部分上形成翅片特征; 在所述翅片特征的第一部分上形成多晶硅的第一区域; 在鳍片特征的第二部分上形成多晶硅的第二区域; 在所述翅片特征的第三部分上形成多晶硅的第三区域，其中所述多晶硅的所述第三区域设置在（i）所述第一区域和（ii）所述第二区域之间; 在所述第一区域和所述第三区域之间形成第一间隔区域; 在所述第二区域和所述第三区域之间形成第二间隔区域; 去除第三区域和形成在第三区域下方的翅片特征的至少一部分，从而形成间隙; 以及将第二电介质材料设置在间隙中以形成隔离部件。

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