Patent search ap:("Marvell World Trade Ltd.") AND inv:"Scott Wu" Page 1

1.

发明授权
Recessed semiconductor substrates and associated techniques 有权

公开(公告)号：US09391045B2

公开(公告)日：2016-07-12

申请号：US14715170

申请日：2015-05-18

Applicant: Marvell World Trade Ltd.

Inventor： Albert Wu , Roawen Chen , Chung Chyung (Justin) Han , Shiann-Ming Liou , Chien-Chuan Wei , Runzi Chang , Scott Wu , Chuan-Cheng Cheng

IPC: H01L21/00 , H01L25/04 , H01L21/48 , H01L23/13 , H01L23/14 , H01L23/498 , H01L25/065 , H01L25/10 , H01L25/00 , H01L23/367 , H01L23/00

CPC classification number: H01L25/04 , H01L21/486 , H01L21/565 , H01L21/76877 , H01L21/76898 , H01L23/13 , H01L23/147 , H01L23/3677 , H01L23/49827 , H01L23/49833 , H01L23/49838 , H01L24/09 , H01L24/16 , H01L24/17 , H01L24/33 , H01L24/48 , H01L24/73 , H01L24/81 , H01L25/0652 , H01L25/0655 , H01L25/0657 , H01L25/105 , H01L25/50 , H01L2224/02372 , H01L2224/0401 , H01L2224/05624 , H01L2224/05647 , H01L2224/13024 , H01L2224/14181 , H01L2224/16225 , H01L2224/16235 , H01L2224/16238 , H01L2224/32225 , H01L2224/48227 , H01L2224/73265 , H01L2224/81193 , H01L2224/83904 , H01L2225/06517 , H01L2225/06527 , H01L2225/06541 , H01L2225/1023 , H01L2225/1058 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , H01L2924/1515 , H01L2924/15153 , H01L2924/15156 , H01L2924/15159 , H01L2924/15311 , H01L2924/1532 , H01L2924/15331 , H01L2924/181 , H01L2924/19042 , H01L2924/19043 , H01L2924/19105 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207

Abstract: Embodiments of the present disclosure provide a method, comprising providing a semiconductor substrate having (i) a first surface and (ii) a second surface that is disposed opposite to the first surface, forming one or more vias in the first surface of the semiconductor substrate, the one or more vias initially passing through only a portion of the semiconductor substrate without reaching the second surface, forming a dielectric film on the first surface of the semiconductor substrate, forming a redistribution layer on the dielectric film, the redistribution layer being electrically coupled to the one or more vias, coupling one or more dies to the redistribution layer, forming a molding compound to encapsulate at least a portion of the one or more dies, and recessing the second surface of the semiconductor substrate to expose the one or more vias. Other embodiments may be described and/or claimed.

2.

发明申请
RECESSED SEMICONDUCTOR SUBSTRATES AND ASSOCIATED TECHNIQUES 审中-公开
Title translation: 残留的半导体衬底和相关技术

公开(公告)号：US20150279806A1

公开(公告)日：2015-10-01

申请号：US14715170

申请日：2015-05-18

Applicant: Marvell World Trade Ltd.

Inventor： Albert Wu , Roawen Chen , Chung Chyung (Justin) Han , Shiann-Ming Liou , Chien-Chuan Wei , Runzi Chang , Scott Wu , Chuan-Cheng Cheng

IPC: H01L23/00

CPC classification number: H01L25/04 , H01L21/486 , H01L21/565 , H01L21/76877 , H01L21/76898 , H01L23/13 , H01L23/147 , H01L23/3677 , H01L23/49827 , H01L23/49833 , H01L23/49838 , H01L24/09 , H01L24/16 , H01L24/17 , H01L24/33 , H01L24/48 , H01L24/73 , H01L24/81 , H01L25/0652 , H01L25/0655 , H01L25/0657 , H01L25/105 , H01L25/50 , H01L2224/02372 , H01L2224/0401 , H01L2224/05624 , H01L2224/05647 , H01L2224/13024 , H01L2224/14181 , H01L2224/16225 , H01L2224/16235 , H01L2224/16238 , H01L2224/32225 , H01L2224/48227 , H01L2224/73265 , H01L2224/81193 , H01L2224/83904 , H01L2225/06517 , H01L2225/06527 , H01L2225/06541 , H01L2225/1023 , H01L2225/1058 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , H01L2924/1515 , H01L2924/15153 , H01L2924/15156 , H01L2924/15159 , H01L2924/15311 , H01L2924/1532 , H01L2924/15331 , H01L2924/181 , H01L2924/19042 , H01L2924/19043 , H01L2924/19105 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207

Abstract: Embodiments of the present disclosure provide a method, comprising providing a semiconductor substrate having (i) a first surface and (ii) a second surface that is disposed opposite to the first surface, forming one or more vias in the first surface of the semiconductor substrate, the one or more vias initially passing through only a portion of the semiconductor substrate without reaching the second surface, forming a dielectric film on the first surface of the semiconductor substrate, forming a redistribution layer on the dielectric film, the redistribution layer being electrically coupled to the one or more vias, coupling one or more dies to the redistribution layer, forming a molding compound to encapsulate at least a portion of the one or more dies, and recessing the second surface of the semiconductor substrate to expose the one or more vias. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例提供一种方法，包括提供半导体衬底，其具有（i）第一表面和（ii）与第一表面相对设置的第二表面，在半导体衬底的第一表面中形成一个或多个通孔一个或多个通孔最初仅通过半导体衬底的一部分而不到达第二表面，在半导体衬底的第一表面上形成电介质膜，在电介质膜上形成再分布层，再分配层电耦合连接到所述一个或多个通孔，将一个或多个管芯耦合到所述再分布层，形成模制化合物以封装所述一个或多个管芯的至少一部分，以及使所述半导体衬底的所述第二表面凹陷以暴露所述一个或多个通孔。可以描述和/或要求保护其他实施例。

3.

发明授权
Structures embedded within core material and methods of manufacturing thereof 有权
Title translation: 嵌入核心材料的结构及其制造方法

公开(公告)号：US09087835B2

公开(公告)日：2015-07-21

申请号：US14140149

申请日：2013-12-24

Applicant: Marvell World Trade Ltd.

Inventor： Sehat Sutardja , Albert Wu , Scott Wu

IPC: H01L23/00 , H01L25/00 , H01L23/31 , H01L23/12 , H01L23/498 , H01L23/48 , H01L23/538 , H01L25/065 , H01L25/18

CPC classification number: H01L25/50 , H01L23/12 , H01L23/3114 , H01L23/481 , H01L23/49822 , H01L23/49827 , H01L23/5389 , H01L24/24 , H01L24/25 , H01L24/48 , H01L24/73 , H01L25/0652 , H01L25/0657 , H01L25/18 , H01L2224/16225 , H01L2224/16227 , H01L2224/16235 , H01L2224/24051 , H01L2224/24226 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/73204 , H01L2224/73253 , H01L2224/73259 , H01L2224/73267 , H01L2224/92224 , H01L2225/06524 , H01L2225/06541 , H01L2225/06582 , H01L2225/06589 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/16152 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207

Abstract: Embodiments of the present disclosure provide a method that comprises providing a first die having a surface comprising a bond pad to route electrical signals of the first die and attaching the first die to a layer of a substrate. The method further comprises forming one or more additional layers of the substrate to embed the first die in the substrate and coupling a second die to the one or more additional layers, the second die having a surface comprising a bond pad to route electrical signals of the second die. The second die is coupled to the one or more additional layers such that electrical signals are routed between the first die and the second die.

Abstract translation: 本公开的实施例提供了一种方法，其包括提供第一管芯，其具有包括接合焊盘的表面以路由第一管芯的电信号并将第一管芯附接到衬底层。该方法还包括形成基板的一个或多个附加层以将第一管芯嵌入衬底中并将第二管芯耦合到一个或多个附加层，第二管芯具有包括接合焊盘的表面，以将电信号第二次死亡第二管芯耦合到一个或多个附加层，使得电信号在第一管芯和第二管芯之间布线。

4.

发明申请
STRUCTURES EMBEDDED WITHIN CORE MATERIAL AND METHODS OF MANUFACTURING THEREOF 审中-公开
Title translation: 在核心材料中嵌入的结构及其制造方法

公开(公告)号：US20140106508A1

公开(公告)日：2014-04-17

申请号：US14140149

申请日：2013-12-24

Applicant: Marvell World Trade Ltd.

Inventor： Sehat Sutardja , Albert Wu , Scott Wu

IPC: H01L25/00

CPC classification number: H01L25/50 , H01L23/12 , H01L23/3114 , H01L23/481 , H01L23/49822 , H01L23/49827 , H01L23/5389 , H01L24/24 , H01L24/25 , H01L24/48 , H01L24/73 , H01L25/0652 , H01L25/0657 , H01L25/18 , H01L2224/16225 , H01L2224/16227 , H01L2224/16235 , H01L2224/24051 , H01L2224/24226 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/73204 , H01L2224/73253 , H01L2224/73259 , H01L2224/73267 , H01L2224/92224 , H01L2225/06524 , H01L2225/06541 , H01L2225/06582 , H01L2225/06589 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/16152 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207

Abstract: Embodiments of the present disclosure provide a method that comprises providing a first die having a surface comprising a bond pad to route electrical signals of the first die and attaching the first die to a layer of a substrate. The method further comprises forming one or more additional layers of the substrate to embed the first die in the substrate and coupling a second die to the one or more additional layers, the second die having a surface comprising a bond pad to route electrical signals of the second die. The second die is coupled to the one or more additional layers such that electrical signals are routed between the first die and the second die.

Abstract translation: 本公开的实施例提供了一种方法，其包括提供第一管芯，其具有包括接合焊盘的表面以路由第一管芯的电信号并将第一管芯附接到衬底层。该方法还包括形成基板的一个或多个附加层以将第一管芯嵌入衬底中并将第二管芯耦合到一个或多个附加层，第二管芯具有包括接合焊盘的表面，以将电信号第二次死亡第二管芯耦合到一个或多个附加层，使得电信号在第一管芯和第二管芯之间布线。

5.

发明申请
MULTI-TEST TYPE PROBE CARD AND CORRESPONDING TESTING SYSTEM FOR PARALLEL TESTING OF DIES VIA MULTIPLE TEST SITES 审中-公开

公开(公告)号：US20180356444A1

公开(公告)日：2018-12-13

申请号：US15996681

申请日：2018-06-04

Applicant: Marvell World Trade Ltd.

Inventor： David Ganapol , Michael Goina , Scott Wu , Marc Jacobs

IPC: G01R1/073 , G01R31/28 , G01R35/00

CPC classification number: G01R1/07307 , G01R31/2887 , G01R35/00

Abstract: A probe card for testing dies of a substrate during a wafer sort process includes a printed circuit board (PCB) and a test site arranged to connect respectively to one of the dies during a test cycle. The test site includes a first pin connecting band and a first pin set. The first pin connecting band is connected to the PCB. The first pin set is connected to the first pin connecting band and includes a pin configuration for a testing device to perform a first type of test on a first die. The test site includes only pins in the first pin set. A number of pins in the first pin set is less than a number of pins used to perform a second type of test on the first die. The second type of test is performed at a slower processing speed than the first type of test.

6.

发明授权
Method and apparatus for improving the reliability of a connection to a via in a substrate 有权

公开(公告)号：US09659851B2

公开(公告)日：2017-05-23

申请号：US14613218

申请日：2015-02-03

Applicant: Marvell World Trade Ltd.

Inventor： Long-Ching Wang , Albert Wu , Scott Wu

IPC: H01L23/13 , H01L23/49 , H05K1/18 , H01L23/498 , H01L21/48 , H05K1/03 , H05K1/11

CPC classification number: H01L23/49827 , H01L21/4853 , H01L21/486 , H01L23/13 , H01L23/49811 , H01L23/49866 , H01L2224/11 , H05K1/0306 , H05K1/115 , H05K1/181 , H05K2201/09563 , H05K2201/10242 , H05K2201/10378 , Y10T29/49165

Abstract: Some of the embodiments of the present disclosure provide a semiconductor package interposer comprising a substrate having a first surface and a second surface, a plurality of vias extending between the first surface and the second surface of the substrate, the plurality of vias electrically connecting electrical connectors or circuitry on the first surface of the substrate to electrical connectors or circuitry on the second surface of the substrate, and metal plugs at least partially filling the plurality of vias. At least one of (i) the first surface or (ii) the second surface of the substrate includes depressions at distal ends of the metal plugs.

7.

发明申请
PACKAGE ASSEMBLY INCLUDING A SEMICONDUCTOR SUBSTRATE IN WHICH A FIRST PORTION OF A SURFACE OF THE SEMICONDUCTOR SUBSTRATE IS RECESSED RELATIVE TO A SECOND PORTION OF THE SURFACE OF THE SEMICONDUCTOR SUBSTRATE TO FORM A RECESSED REGION IN THE SEMICONDUCTOR SUBSTRATE 审中-公开
Title translation: 封装组件包括半导体衬底，其中半导体衬底的表面的第一部分相对于半导体衬底的表面的第二部分被覆盖以形成半导体衬底中的凹陷区域

公开(公告)号：US20160155732A1

公开(公告)日：2016-06-02

申请号：US15017397

申请日：2016-02-05

Applicant: Marvell World Trade Ltd.

Inventor： Albert Wu , Roawen Chen , Chung Chyung (Justin) Han , Shiann-Ming Liou , Chien-Chuan Wei , Runzi Chang , Scott Wu , Chuan-Cheng Cheng

IPC: H01L25/00 , H01L21/48 , H01L21/56 , H01L25/065 , H01L23/498 , H01L21/768 , H01L23/00

CPC classification number: H01L25/04 , H01L21/486 , H01L21/565 , H01L21/76877 , H01L21/76898 , H01L23/13 , H01L23/147 , H01L23/3677 , H01L23/49827 , H01L23/49833 , H01L23/49838 , H01L24/09 , H01L24/16 , H01L24/17 , H01L24/33 , H01L24/48 , H01L24/73 , H01L24/81 , H01L25/0652 , H01L25/0655 , H01L25/0657 , H01L25/105 , H01L25/50 , H01L2224/02372 , H01L2224/0401 , H01L2224/05624 , H01L2224/05647 , H01L2224/13024 , H01L2224/14181 , H01L2224/16225 , H01L2224/16235 , H01L2224/16238 , H01L2224/32225 , H01L2224/48227 , H01L2224/73265 , H01L2224/81193 , H01L2224/83904 , H01L2225/06517 , H01L2225/06527 , H01L2225/06541 , H01L2225/1023 , H01L2225/1058 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , H01L2924/1515 , H01L2924/15153 , H01L2924/15156 , H01L2924/15159 , H01L2924/15311 , H01L2924/1532 , H01L2924/15331 , H01L2924/181 , H01L2924/19042 , H01L2924/19043 , H01L2924/19105 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207

Abstract: Embodiments of the present disclosure provide an apparatus comprising a semiconductor substrate having a first surface, a second surface that is disposed opposite to the first surface, wherein at least a portion of the first surface is recessed to form a recessed region of the semiconductor substrate, and one or more vias formed in the recessed region of the semiconductor substrate to provide an electrical or thermal pathway between the first surface and the second surface of the semiconductor substrate, and a die coupled to the semiconductor substrate, the die being electrically coupled to the one or more vias formed in the recessed region of the semiconductor substrate. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例提供了一种装置，包括具有第一表面的半导体衬底，与第一表面相对设置的第二表面，其中第一表面的至少一部分被凹入以形成半导体衬底的凹陷区域，以及形成在半导体衬底的凹陷区域中以在半导体衬底的第一表面和第二表面之间提供电或热路径的一个或多个通孔，以及耦合到半导体衬底的管芯，该管芯电耦合到形成在半导体衬底的凹陷区域中的一个或多个通孔。可以描述和/或要求保护其他实施例。

8.

发明申请
HEAT SINK BLADE PACK FOR DEVICE UNDER TEST TESTING 有权
Title translation: 用于测试测试装置的散热叶片组

公开(公告)号：US20140132296A1

公开(公告)日：2014-05-15

申请号：US14076058

申请日：2013-11-08

Applicant: Marvell World Trade Ltd.

Inventor： Bruce Tirado , Scott Wu , William Su , David Ganapol , Robert P. Zaldain , Reid T. Hirata , Tom Lim

IPC: G01R31/00 , G01R31/26

CPC classification number: G01R31/003 , G01R31/2601 , G01R31/2867 , G01R31/2877

Abstract: Embodiments of the present disclosure provide an apparatus configured to engage a device for testing the device via automatic test equipment. The apparatus includes a heat sink, wherein the heat sink comprises a plurality of fins extending from the heat sink, and wherein the heat sink is configured to engage the device. The apparatus further includes a heat conduction layer coupled to the heat sink, a first leg coupled to the heat conduction layer, and a second leg coupled to the heat conduction layer. The second leg is spaced apart from the first leg. A vacuum path is defined through (i) the heat conduction layer and (ii) the heat sink. The vacuum path permits the apparatus to engage the device to be tested by the automatic test equipment.

Abstract translation: 本公开的实施例提供了一种被配置为接合用于经由自动测试设备测试该设备的设备的设备。该设备包括散热器，其中散热器包括从散热器延伸的多个散热片，并且其中散热器被配置为接合设备。该装置还包括耦合到散热器的热传导层，耦合到导热层的第一支腿和耦合到导热层的第二支脚。第二条腿与第一条腿分开。通过（i）导热层和（ii）散热器来定义真空路径。真空路径允许设备通过自动测试设备接合要测试的设备。

9.

发明申请
TECHNIQUES AND CONFIGURATIONS FOR RECESSED SEMICONDUCTOR SUBSTRATES 审中-公开
Title translation: 接触半导体衬底的技术和配置

公开(公告)号：US20140124961A1

公开(公告)日：2014-05-08

申请号：US14153892

申请日：2014-01-13

Applicant: Marvell World Trade Ltd.

Inventor： Albert WU , Roawen Chen , Chung Chyung Han , Shiann-Ming Liou , Chien-Chuan Wei , Runzi Chang , Scott Wu , Chuan-Cheng Cheng

IPC: H01L25/04

CPC classification number: H01L25/04 , H01L21/486 , H01L21/565 , H01L21/76877 , H01L21/76898 , H01L23/13 , H01L23/147 , H01L23/3677 , H01L23/49827 , H01L23/49833 , H01L23/49838 , H01L24/09 , H01L24/16 , H01L24/17 , H01L24/33 , H01L24/48 , H01L24/73 , H01L24/81 , H01L25/0652 , H01L25/0655 , H01L25/0657 , H01L25/105 , H01L25/50 , H01L2224/02372 , H01L2224/0401 , H01L2224/05624 , H01L2224/05647 , H01L2224/13024 , H01L2224/14181 , H01L2224/16225 , H01L2224/16235 , H01L2224/16238 , H01L2224/32225 , H01L2224/48227 , H01L2224/73265 , H01L2224/81193 , H01L2224/83904 , H01L2225/06517 , H01L2225/06527 , H01L2225/06541 , H01L2225/1023 , H01L2225/1058 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , H01L2924/1515 , H01L2924/15153 , H01L2924/15156 , H01L2924/15159 , H01L2924/15311 , H01L2924/1532 , H01L2924/15331 , H01L2924/181 , H01L2924/19042 , H01L2924/19043 , H01L2924/19105 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207

Abstract: Embodiments of the present disclosure provide a method comprising providing a semiconductor substrate having (i) a first surface and (ii) a second surface that is disposed opposite to the first surface, forming a dielectric film on the first surface of the semiconductor substrate, forming a redistribution layer on the dielectric film, electrically coupling one or more dies to the redistribution layer, forming a molding compound on the semiconductor substrate, recessing the second surface of the semiconductor substrate, forming one or more channels through the recessed second surface of the semiconductor substrate to expose the redistribution layer; and forming one or more package interconnect structures in the one or more channels, the one or more package interconnect structures being electrically coupled to the redistribution layer, the one or more package interconnect structures to route electrical signals of the one or more dies. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例提供了一种方法，包括提供具有（i）第一表面和（ii）与第一表面相对设置的第二表面的半导体衬底，在半导体衬底的第一表面上形成电介质膜，形成电介质膜上的再分配层，将一个或多个管芯电耦合到再分布层，在半导体衬底上形成模制化合物，使半导体衬底的第二表面凹陷，通过半导体的凹陷的第二表面形成一个或多个沟道衬底以暴露再分布层; 以及在所述一个或多个通道中形成一个或多个封装互连结构，所述一个或多个封装互连结构电耦合到所述再分布层，所述一个或多个封装互连结构用于布置所述一个或多个管芯的电信号。可以描述和/或要求保护其他实施例。