公开(公告)号：US09614539B2

公开(公告)日：2017-04-04

申请号：US15130302

申请日：2016-04-15

Applicant: MaxLinear, Inc.

Inventor： Yongjian Tang

IPC: H03M1/38 ,  H03M1/46 ,  H03M1/00 ,  H03M1/12 ,  H03M1/06

CPC classification number: H03M1/466 ,  H03M1/00 ,  H03M1/0695 ,  H03M1/12 ,  H03M1/125

Abstract: Systems and methods are provided for a successive approximation register (SAR) analog-to-digital converter (ADC) with an ultra-low burst error rate. Analog-to-digital conversions may be applied via a plurality of successive conversion cycles, with each conversion cycle corresponding to a particular bit in a corresponding digital output. Meta-stability may be detected during each one of the plurality of successive conversion cycles, and for each one of the plurality of successive conversion cycles, a next one of the plurality of successive conversion cycles may be triggered based on a cycle termination event. After completion of all of the plurality of successive conversion cycles, a meta-stability state of each of the plurality of successive conversion cycles may be assessed, and the digital output may be controlled based on the assessment.

公开(公告)号：US20160308550A1

公开(公告)日：2016-10-20

申请号：US15130302

申请日：2016-04-15

Applicant: MaxLinear, Inc.

Inventor： Yongjian Tang

IPC: H03M1/46

CPC classification number: H03M1/466 ,  H03M1/00 ,  H03M1/0695 ,  H03M1/12 ,  H03M1/125

Abstract: Systems and methods are provided for a successive approximation register (SAR) analog-to-digital converter (ADC) with an ultra-low burst error rate. Analog-to-digital conversions may be applied via a plurality of successive conversion cycles, with each conversion cycle corresponding to a particular bit in a corresponding digital output. Meta-stability may be detected during each one of the plurality of successive conversion cycles, and for each one of the plurality of successive conversion cycles, a next one of the plurality of successive conversion cycles may be triggered based on a cycle termination event. After completion of all of the plurality of successive conversion cycles, a meta-stability state of each of the plurality of successive conversion cycles may be assessed, and the digital output may be controlled based on the assessment.

Abstract translation: 为具有超低突发错误率的逐次逼近寄存器（SAR）模数转换器（ADC）提供系统和方法。 可以经由多个连续的转换周期来应用模数转换，其中每个转换周期对应于相应的数字输出中的特定位。 可以在多个连续转换周期中的每一个期间检测元稳定性，并且对于多个连续转换周期中的每一个，可以基于循环终止事件来触发多个连续转换周期中的下一个。 在完成所有多个连续转换周期之后，可以评估多个连续转换周期中的每一个的元稳定状态，并且可以基于评估来控制数字输出。

公开(公告)号：US20180234106A1

公开(公告)日：2018-08-16

申请号：US15935567

申请日：2018-03-26

Applicant: MaxLinear, Inc.

Inventor： Yongjian Tang

IPC: H03M1/46 ,  H03M1/12 ,  H03M1/00 ,  H03M1/06

CPC classification number: H03M1/466 ,  H03M1/00 ,  H03M1/0695 ,  H03M1/12 ,  H03M1/125

Abstract: Systems and methods are provided for enhanced analog-to-digital conversions, particularly by allowing for an ultra-low burst error rate. Analog-to-digital conversion may be applied to an analog input via one or more conversion cycles; and performance related parameter corresponding to the analog-to-digital conversion may be assessed. A digital output corresponding to the analog input may be generated, with the generating being controlled based on the assessing of the performance related parameter. The controlling may include adjusting at least a portion of the digital output. The assessing may include determining, for at least one conversion cycle, whether a performance related condition, corresponding to the performance related parameter, occurs. The determination may be based on an outcome of a matching search performed for that conversion cycle. The determination that the performance related condition occurs may be made when the matching search fails to settle within a corresponding time period.

公开(公告)号：US09813052B2

公开(公告)日：2017-11-07

申请号：US15444662

申请日：2017-02-28

Applicant: Maxlinear, Inc.

Inventor： Yongjian Tang ,  Xuefeng Chen

IPC: H03K17/16 ,  H03K17/06

CPC classification number: H03K17/063 ,  H03K17/687 ,  H03K2217/0054

Abstract: Methods and systems for reliable bootstrapping switches may comprise sampling a received signal with a bootstrapping switch, where the bootstrapping switch comprises a switching metal-oxide semiconductor (MOS) transistor having a pull-down path coupled to a gate terminal of the switching MOS transistor, wherein: source terminals of both a diode-connected transistor and a second MOS transistor are coupled to the gate terminal of the switching MOS transistor; drain terminals of both the diode-connected transistor and the second MOS transistor are coupled to a source terminal of a third MOS transistor, the third MOS transistor coupled in series with a fourth MOS transistor; and a drain terminal of the fourth MOS transistor is coupled to ground. The third and fourth MOS transistors may be in series with the second MOS transistor. A gate terminal of the fourth transistor may be switched from ground to a supply voltage to activate the pull-down path.

公开(公告)号：US09780799B2

公开(公告)日：2017-10-03

申请号：US14939473

申请日：2015-11-12

Applicant: Maxlinear, Inc.

Inventor： Yongjian Tang ,  Hao Liu

IPC: H03M1/12 ,  H03M1/06 ,  H03M1/44

CPC classification number: H03M1/0609 ,  H03M1/0607 ,  H03M1/0682 ,  H03M1/1245 ,  H03M1/442 ,  H03M1/468

Abstract: Methods and systems for an analog-to-digital converter (ADC) with constant common mode voltage may include in an ADC comprising a sampling switch on a first input line to the ADC, a sampling switch on a second input line to the ADC, N switched capacitor pairs and M single switched capacitors on the first input line, and N switched capacitor pairs and M single switched capacitors on the second input line: sampling an input voltage by closing the sampling switches, opening the sampling switches and comparing voltage levels between the input lines, iteratively switching the switched capacitor pairs between a reference voltage (Vref) and ground based on the compared voltage levels, and iteratively switching the single switched capacitors between ground and voltages that are a fraction of Vref, which may equal Vref/2x where x ranges from 0 to m−1 and m is a number of single switched capacitors per input line.

公开(公告)号：US20170141784A1

公开(公告)日：2017-05-18

申请号：US14939473

申请日：2015-11-12

Applicant: Maxlinear, Inc.

Inventor： Yongjian Tang ,  Hao Liu

IPC: H03M1/06 ,  H03M1/44

CPC classification number: H03M1/0609 ,  H03M1/0607 ,  H03M1/0682 ,  H03M1/1245 ,  H03M1/442 ,  H03M1/468

Abstract: Methods and systems for an analog-to-digital converter (ADC) with constant common mode voltage may include in an ADC comprising a sampling switch on a first input line to the ADC, a sampling switch on a second input line to the ADC, N switched capacitor pairs and M single switched capacitors on the first input line, and N switched capacitor pairs and M single switched capacitors on the second input line: sampling an input voltage by closing the sampling switches, opening the sampling switches and comparing voltage levels between the input lines, iteratively switching the switched capacitor pairs between a reference voltage (Vref) and ground based on the compared voltage levels, and iteratively switching the single switched capacitors between ground and voltages that are a fraction of Vref, which may equal Vref/2x where x ranges from 0 to m−1 and m is a number of single switched capacitors per input line.

公开(公告)号：US20170111052A1

公开(公告)日：2017-04-20

申请号：US15395586

申请日：2016-12-30

Applicant: Maxlinear, Inc.

Inventor： Hao Liu ,  Yongjian Tang

IPC: H03M1/06 ,  H03M1/66 ,  H03M1/12

CPC classification number: H03M1/0678 ,  H03H19/004 ,  H03M1/0604 ,  H03M1/12 ,  H03M1/66

Abstract: Methods and systems for charge compensation for switched-capacitor circuits may comprise, in an electronics device comprising a first voltage source, a switched capacitor load, and a switched capacitor compensation circuit: switching a capacitor in the switched capacitor load from a first voltage to a second voltage; providing a charge to the switched capacitor load from the switched capacitor compensation circuit without requiring added charge from the first voltage source. A reference voltage may be generated utilizing the first voltage source. A replica reference voltage for the switched capacitor compensation circuit may be generated utilizing a second voltage source. The replica reference voltage may be equal to the reference voltage. The replica reference voltage may be equal to a supply voltage, VDD, for circuitry in the electronics device. Capacitors may couple outputs of the first and second voltage sources to ground.

公开(公告)号：US09584112B2

公开(公告)日：2017-02-28

申请号：US14585707

申请日：2014-12-30

Applicant: Maxlinear, Inc.

Inventor： Yongjian Tang ,  Xuefeng Chen

IPC: H03K17/16 ,  H03K17/687 ,  H03K17/06

CPC classification number: H03K17/063 ,  H03K17/687 ,  H03K2217/0054

Abstract: Methods and systems for reliable bootstrapping switches may comprise sampling a received signal with a bootstrapping switch, where the bootstrapping switch comprises a switching metal-oxide semiconductor (MOS) transistor having a pull-down path coupled to a gate terminal of the switching MOS transistor. The pull-down path includes a diode-connected MOS transistor coupled in parallel with a second MOS transistor that couples the gate terminal of the switching MOS transistor to ground via third and fourth MOS transistors when the switching MOS transistor is in an OFF state. The third and fourth MOS transistors may be in series with the second MOS transistor. A gate terminal of the fourth transistor may be switched from ground to a supply voltage, VDD, to activate the pull-down path. A capacitor may be coupled between gate and source terminals of the switching MOS transistor to switch the switching MOS transistor to an ON state.

Abstract translation: 用于可靠自举开关的方法和系统可以包括用自举开关对接收到的信号进行采样，其中自举开关包括具有耦合到开关MOS晶体管的栅极端子的下拉通路的开关金属氧化物半导体（MOS）晶体管。 下拉路径包括与第二MOS晶体管并联耦合的二极管连接的MOS晶体管，当开关MOS晶体管处于截止状态时，第二MOS晶体管通过第三和第四MOS晶体管将开关MOS晶体管的栅极端子接地。 第三和第四MOS晶体管可以与第二MOS晶体管串联。 第四晶体管的栅极端子可以从地切换到电源电压VDD，以激活下拉路径。 电容器可以耦合在开关MOS晶体管的栅极和源极端子之间，以将开关MOS晶体管切换到导通状态。

公开(公告)号：US20150194981A1

公开(公告)日：2015-07-09

申请号：US14592020

申请日：2015-01-08

Applicant: Maxlinear, Inc.

Inventor： Yongjian Tang ,  Hao Liu

IPC: H03M1/44 ,  H03M1/12

CPC classification number: H03M1/0609 ,  H03M1/0607 ,  H03M1/0682 ,  H03M1/1245 ,  H03M1/442 ,  H03M1/468

Abstract: Methods and systems for an analog-to-digital converter with near-constant common mode voltage may comprise, in an analog-to-digital converter (ADC) having sampling switches on each of two input lines to the ADC, N double-sided and M single-sided switched capacitors on each input line: sampling an input voltage by closing the sampling switches, opening the sampling switches and comparing voltage levels between the input lines, iteratively switching the double-sided switched capacitors between a reference voltage (Vref) and ground, and iteratively switching the single-sided switched capacitors between ground and voltages that may equal Vref/2x where x ranges from 0 to m−1 and m is a number of single-sided switched capacitors per input line. A common mode offset of the ADC may be less than VADC—fs/128 +VADC—fs/256+VADC—fs/512+VADC—fs/1024 when m equals 4 and where VADC—fs is the full-scale voltage of the ADC.

Abstract translation: 具有近常数共模电压的模数转换器的方法和系统可以包括在具有到ADC的两个输入线中的每一个上的采样开关的模数转换器（ADC）中，N个双面和 每个输入线上的M个单面开关电容器：通过关闭采样开关来采样输入电压，打开采样开关并比较输入线路之间的电压电平，将双侧开关电容器在参考电压（Vref）和 接地并迭代地切换接地和电压之间的单侧开关电容，其可以等于Vref / 2x，其中x的范围从0到m-1，而m是每个输入线的单侧开关电容的数量。 当m等于4时，ADC的共模偏移可能小于VADC-fs / 128 + VADC-fs / 256 + VADC-fs / 512 + VADC-fs / 1024，其中VADC-fs是 ADC。

公开(公告)号：US20200036387A1

公开(公告)日：2020-01-30

申请号：US16589907

申请日：2019-10-01

Applicant: MaxLinear, Inc.

Inventor： Yongjian Tang

IPC: H03M1/46 ,  H03M1/12

Abstract: Systems and methods are provided for a successive approximation register (SAR) analog-to-digital converter (ADC) with an ultra-low burst error rate. Analog-to-digital conversions may be applied via a plurality of successive conversion cycles, with each conversion cycle corresponding to a particular bit in a corresponding digital output. Meta-stability may be detected during each one of the plurality of successive conversion cycles, and for each one of the plurality of successive conversion cycles, a next one of the plurality of successive conversion cycles may be triggered based on a cycle termination event. After completion of all of the plurality of successive conversion cycles, a meta-stability state of each of the plurality of successive conversion cycles may be assessed, and the digital output may be controlled based on the assessment.