公开(公告)号：US12176045B2

公开(公告)日：2024-12-24

申请号：US17659402

申请日：2022-04-15

Applicant: Micron Technology, Inc.

Inventor： Binbin Huo

IPC: G11C16/34 ,  G11C16/16 ,  G11C16/26

Abstract: Methods, systems, and devices for techniques to retire unreliable blocks are described. A memory system may receive a request for information about a quantity of erase operations performed on a block of the memory system. Based on the request, the memory system may determine the quantity of erase operations performed on the block and transmit an indication of the quantity of erase operations performed on the block.

公开(公告)号：US20230409477A1

公开(公告)日：2023-12-21

申请号：US18239969

申请日：2023-08-30

Applicant: Micron Technology, Inc.

Inventor： Vincenzo Reina ,  Binbin Huo

IPC: G06F12/0804 ,  G01K3/06

CPC classification number: G06F12/0804 ,  G01K3/06 ,  G06F2212/1032

Abstract: Methods, systems, and devices for advanced power off notification for managed memory are described. An apparatus may include a memory array comprising a plurality of memory cells and a controller coupled with the memory array. The controller may be configured to receive a notification indicating a transition from a first state of the memory array to a second state of the memory array. The notification may include a value, the value comprising a plurality of bits and corresponding to a minimum duration remaining until a power supply of the memory array is deactivated. The controller may also execute a plurality of operations according to an order determined based at least in part on a parameter associated with the memory array and receiving the notification comprising the value.

公开(公告)号：US11762771B2

公开(公告)日：2023-09-19

申请号：US17241850

申请日：2021-04-27

Applicant: Micron Technology, Inc.

Inventor： Vincenzo Reina ,  Binbin Huo

IPC: G06F12/0804 ,  G01K3/06

CPC classification number: G06F12/0804 ,  G01K3/06 ,  G06F2212/1032

Abstract: Methods, systems, and devices for advanced power off notification for managed memory are described. An apparatus may include a memory array comprising a plurality of memory cells and a controller coupled with the memory array. The controller may be configured to receive a notification indicating a transition from a first state of the memory array to a second state of the memory array. The notification may include a value, the value comprising a plurality of bits and corresponding to a minimum duration remaining until a power supply of the memory array is deactivated. The controller may also execute a plurality of operations according to an order determined based at least in part on a parameter associated with the memory array and receiving the notification comprising the value.

公开(公告)号：US20250094303A1

公开(公告)日：2025-03-20

申请号：US18467267

申请日：2023-09-14

Applicant: Micron Technology, Inc.

Inventor： Binbin Huo ,  Olivier Duval

IPC: G06F11/30 ,  G06F11/34 ,  G06F13/16

Abstract: Methods, systems, and devices for host system diagnostic testing are described. A diagnostic tool including a diagnostic executable stored to an external memory may evaluate a system including a host subsystem and a memory subsystem. Upon initialization, the diagnostic executable may configure trace points in one or more layers (e.g., associated with an operating system) of the host subsystem based on dependencies (e.g., libraries) stored to the external memory, and may receive, from the host subsystem, first data collected at the trace points, directly from a host system buffer, or from the memory subsystem. Concurrent to the collection procedure, the diagnostic executable may perform processing operations on the first data to generate second data, which may be associated with one or more metrics of system performance. The second data is stored to the external memory, and may be utilized to evaluate the system.

公开(公告)号：US11971816B2

公开(公告)日：2024-04-30

申请号：US17838832

申请日：2022-06-13

Applicant: Micron Technology, Inc.

Inventor： Binbin Huo

IPC: G06F12/02 ,  G06F12/0817 ,  G06F12/0873 ,  G06F12/0882

CPC classification number: G06F12/0246 ,  G06F12/0253 ,  G06F12/0822 ,  G06F12/0873 ,  G06F12/0882 ,  G06F2212/7201

Abstract: Various embodiments enable sending a notification to a host system based on an address mapping entry miss (or mismatch) on a memory sub-system, which can facilitate an update of one or more address mapping entries stored on the host system.

公开(公告)号：US11748220B2

公开(公告)日：2023-09-05

申请号：US17529775

申请日：2021-11-18

Applicant: Micron Technology, Inc.

Inventor： Rainer F. Bonitz ,  Binbin Huo

IPC: G06F11/07 ,  G06F11/26 ,  G06F3/06 ,  G06F11/30

CPC classification number: G06F11/26 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0679 ,  G06F11/0757 ,  G06F11/0772 ,  G06F11/3034

Abstract: A computing system can comprise a processing resource and a memory device coupled together via a first transmission link. The processing resource can be configured to test the first transmission link in response to the memory device failing to execute a command by sending the command to the memory device again for retry and monitoring the first transmission link for signals that indicate whether the command was executed by the memory device.

公开(公告)号：US11698752B2

公开(公告)日：2023-07-11

申请号：US17111407

申请日：2020-12-03

Applicant: Micron Technology, Inc.

Inventor： Binbin Huo

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0679

Abstract: A method and system for retransmitting messages in a memory subsystem are described. A message is transmitted to a host system. A response message is expected to be received from the host system in response to the message. A determination that the response message was not received prior to detecting an indication of a processing of a number of commands from the host system is performed. The message is retransmitted to the host system in response to the determination.

公开(公告)号：US20230110377A1

公开(公告)日：2023-04-13

申请号：US17500676

申请日：2021-10-13

Applicant: Micron Technology, Inc.

Inventor： Binbin Huo

IPC: G06F3/06

Abstract: Methods, systems, and devices for parameter table protection for a memory system are described. Upon booting a memory system for a first time, the memory system or a host system may generate an error control code associated with parameter data stored to the memory system. The error control code may be stored to the memory system and may be configured to correct one or more errors in the parameter data upon subsequent boot sequences of the memory system. Accordingly, upon booting the memory system for a second or a subsequent time, the error control code may be used to identify and correct errors in the parameter data, which may reduce the quantity of copies of parameter data stored to the memory system and may prevent the memory system from experiencing a system crash.

公开(公告)号：US20220342819A1

公开(公告)日：2022-10-27

申请号：US17241850

申请日：2021-04-27

Applicant: Micron Technology, Inc.

Inventor： Vincenzo Reina ,  Binbin Huo

IPC: G06F12/0804 ,  G01K3/06

Abstract: Methods, systems, and devices for advanced power off notification for managed memory are described. An apparatus may include a memory array comprising a plurality of memory cells and a controller coupled with the memory array. The controller may be configured to receive a notification indicating a transition from a first state of the memory array to a second state of the memory array. The notification may include a value, the value comprising a plurality of bits and corresponding to a minimum duration remaining until a power supply of the memory array is deactivated. The controller may also execute a plurality of operations according to an order determined based at least in part on a parameter associated with the memory array and receiving the notification comprising the value.

公开(公告)号：US11301372B1

公开(公告)日：2022-04-12

申请号：US16951986

申请日：2020-11-18

Applicant: Micron Technology, Inc.

Inventor： Binbin Huo

IPC: G06F12/02 ,  G06F12/0882 ,  G06F13/16 ,  G06F12/0868

Abstract: Methods, systems, and devices for host side memory address management are described. In some examples, a host system may identify a read request that includes a logical address of a block of a memory device. The read request may be associated with a descriptor indicating a page of a cache of the host system. The host system may determine to assign a descriptor to a page of the cache, and may recycle one or more pages of the cache. In some examples, the host system may determine whether the page indicated by the descriptor includes a mapping between the logical address and a physical address of the memory device, and may issue a read command to the memory device based on the page including the mapping.