公开(公告)号：US20230378043A1

公开(公告)日：2023-11-23

申请号：US17750140

申请日：2022-05-20

Applicant: Micron Technology, Inc.

Inventor： Chin Hui Chong ,  Seng Kim Ye ,  Kelvin Tan Aik Boo ,  Hong Wan Ng

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49838 ,  H01L21/4846

Abstract: Semiconductor devices with three-dimensional trace matching features, and related systems and methods, are disclosed herein. In some embodiments, an exemplary semiconductor device includes at least one semiconductor die and a redistribution layer disposed over the at least one semiconductor die and extending across a longitudinal plane. The redistribution layer includes first and second traces each electrically coupled to the at least one semiconductor die. The first trace is disposed in a first travel path included in a first effective path length. The second trace is disposed in a second travel path different from the first travel path. The second the second travel path includes at least one segment at a non-right, non-zero angle such that the at least one segment is neither parallel nor perpendicular to the longitudinal plane. Further, the second travel path is included in a second effective path length equal to the first path length.

公开(公告)号：US11723150B2

公开(公告)日：2023-08-08

申请号：US17012817

申请日：2020-09-04

Applicant: Micron Technology, Inc.

Inventor： Kelvin Tan Aik Boo ,  Chin Hui Chong ,  Seng Kim Ye ,  Hong Wan Ng ,  Hem P. Takiar

IPC: H05K1/18 ,  H01L25/065 ,  H01L23/13 ,  H01L23/498 ,  H01L23/64

CPC classification number: H05K1/183 ,  H01L23/13 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/642 ,  H01L25/0657 ,  H05K1/181 ,  H01L23/49816 ,  H05K2201/10015 ,  H05K2201/10159

Abstract: An apparatus includes a primary layer of a substrate that includes an open area that extends through the primary layer to an inner layer of the substrate. The apparatus includes a secondary layer of the substrate. The apparatus also includes the inner layer of the substrate that is positioned between the primary layer and the secondary layer. The inner layer includes component bond pads that are disposed on the inner layer and that are exposed via the open area of the primary layer.

公开(公告)号：US20230061803A1

公开(公告)日：2023-03-02

申请号：US17460126

申请日：2021-08-27

Applicant: Micron Technology, Inc.

Inventor： Ling Pan ,  Sook Har Leong ,  Kelvin Tan Aik Boo

IPC: H01L23/373 ,  H01L25/065 ,  H01L21/50

Abstract: Semiconductor devices and associated systems and methods are disclosed herein. In some embodiments the semiconductor devices include a package substrate, a controller die carried by the package substrate and a spacer carried by the package substrate spaced apart from the controller die. A thermally conductive material can be carried by an upper surface of the controller die and establish a thermal path extending from the upper surface of the controller die to the package substrate. The thermal path can reach the package substrate at a position horizontally between the controller die and the spacer. The semiconductor device can also include one or more dies at least partially carried by the spacer and at least partially above the controller die and the thermally conductive material. Each of the one or more dies is thermally insulated from the thermally conductive material, for example by a thermal adhesive layer between the two.

公开(公告)号：US11527459B2

公开(公告)日：2022-12-13

申请号：US17243466

申请日：2021-04-28

Applicant: Micron Technology, Inc.

Inventor： Hong Wan Ng ,  Chin Hui Chong ,  Hem P. Takiar ,  Seng Kim Ye ,  Kelvin Tan Aik Boo

IPC: H01L29/76 ,  H01L29/00 ,  H01L23/48 ,  H01L27/08 ,  H01L49/02 ,  H01L23/498

Abstract: Substrates for semiconductor packages, including hybrid substrates for decoupling capacitors, and associated devices, systems, and methods are disclosed herein. In one embodiment, a substrate includes a first pair and a second pair of electrical contacts on a first surface of the substrate. The first pair of electrical contacts can be configured to receive a first surface-mount capacitor, and the second pair of electrical contacts can be configured to receive a second surface-mount capacitor. The first pair of electrical contacts can be spaced apart by a first space, and the second pair of electrical contacts can be spaced apart by a second space. The first and second spaces can correspond to first and second distances between electrical contacts of the first and second surface-mount capacitors.

公开(公告)号：US20220078915A1

公开(公告)日：2022-03-10

申请号：US17012817

申请日：2020-09-04

Applicant: Micron Technology, Inc.

Inventor： Kelvin Tan Aik Boo ,  Chin Hui Chong ,  Seng Kim Ye ,  Hong Wan Ng ,  Hem P. Takiar

IPC: H05K1/18 ,  H01L25/065 ,  H01L23/13 ,  H01L23/498 ,  H01L23/64

Abstract: An apparatus includes a primary layer of a substrate that includes an open area that extends through the primary layer to an inner layer of the substrate. The apparatus includes a secondary layer of the substrate. The apparatus also includes the inner layer of the substrate that is positioned between the primary layer and the secondary layer. The inner layer includes component bond pads that are disposed on the inner layer and that are exposed via the open area of the primary layer.

公开(公告)号：US20240312890A1

公开(公告)日：2024-09-19

申请号：US18443166

申请日：2024-02-15

Applicant: Micron Technology, Inc.

Inventor： Kelvin Tan Aik Boo ,  Hong Wan Ng ,  See Hiong Leow ,  Ling Pan ,  Seng Kim Ye ,  Chin Hui Chong

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L23/49838 ,  H01L23/3128 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/50 ,  H01L2224/32225 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73215 ,  H01L2924/181 ,  H01L2924/19011

Abstract: At least one embodiment of a semiconductor device assembly include a cross-stack substrate can comprise an assembly substrate including an upper surface, a first and second die stack at the upper surface, and a cross-stack substrate spaced from the upper surface. The first and second die stacks can each include multiple semiconductor dies in electric communication with the assembly substrate, and the cross-stack substrate can be coupled to and extending between a first and a second semiconductor die of the first and second die stacks, respectively. A passive semiconductor component can be carried by the cross-stack substrate, and can be in electric communication with the assembly substrate. Further, the passive semiconductor component can be in electric communication with the first semiconductor die of the first die stack exclusively via the assembly substrate.

公开(公告)号：US11929351B2

公开(公告)日：2024-03-12

申请号：US17682948

申请日：2022-02-28

Applicant: Micron Technology, Inc.

Inventor： Kelvin Tan Aik Boo ,  Chin Hui Chong ,  Seng Kim Ye ,  Hong Wan Ng ,  Hem P. Takiar

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/498 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L23/49811 ,  H01L23/49822 ,  H01L24/48 ,  H01L24/85 ,  H01L25/50 ,  H01L2224/48228 ,  H01L2224/48229 ,  H01L2224/85045 ,  H01L2225/0651 ,  H01L2225/06562

Abstract: An apparatus includes a substrate for mounting an integrated circuit. The substrate includes a primary layer including a first surface that is a first external surface of the substrate. The substrate includes an inner layer that is located below the primary layer and including a second surface. A portion of the second surface of the inner layer is exposed via an open area associated with the primary layer. The inner layer includes a first multiple of wire bond pads that are exposed via the open area associated with the primary layer.

公开(公告)号：US20240079306A1

公开(公告)日：2024-03-07

申请号：US17930304

申请日：2022-09-07

Applicant: Micron Technology, Inc.

Inventor： Kelvin Tan Aik Boo ,  Wen Wei Lum ,  Hong Wan Ng

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L21/4846 ,  H01L23/49816 ,  H01L23/49894 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/13 ,  H01L24/48 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48225 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/81815 ,  H01L2924/1433 ,  H01L2924/1438 ,  H01L2924/35121

Abstract: A microelectronic device package includes a microelectronic device, a masking material defined (MMD) contact, and a non-masking material defined (NMMD) contact. The microelectronic device is supported on, and electrically connected to, one of a package substrate and a redistribution layer. The MMD contact is located in a first region of the one of the package substrate and the redistribution layer and facilitates a first electrical connection between the microelectronic device and the one of the package substrate and the redistribution layer. The NMMD contact is located in a second, different region of the one of the package substrate and the redistribution layer and facilitates a second electrical connection between the microelectronic device and the one of the package substrate and the redistribution layer. Related methods and systems are also disclosed.

公开(公告)号：US20240072022A1

公开(公告)日：2024-02-29

申请号：US17899592

申请日：2022-08-30

Applicant: Micron Technology, Inc.

Inventor： Seng Kim Ye ,  Kelvin Tan Aik Boo ,  Hong Wan Ng ,  Chin Hui Chong

IPC: H01L25/16 ,  H01G2/06 ,  H01G13/00 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L25/16 ,  H01G2/06 ,  H01G13/00 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0657 ,  H01L25/18 ,  H01L24/16 ,  H01L2224/16225 ,  H01L2224/48106 ,  H01L2224/48145 ,  H01L2224/48195 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06562 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/19041 ,  H01L2924/19105

Abstract: Semiconductor devices, and related systems and methods, are disclosed herein. In some embodiments, the stacked semiconductor device includes a package substrate having an inner surface, a die stack carried by the inner surface, and a stacked capacitor device carried by the inner surface adjacent to the die stack. The die stack can include one or more semiconductor dies, each of which can be electrically coupled to the inner surface by one or more bond wires and/or solder structures. The stacked capacitor device can include a first capacitor having a lower surface attached to the inner surface of the package substrate, a interposer having a first side attached to an upper surface of the first capacitor, and a second capacitor attached to a second side of the interposer opposite the first side.

公开(公告)号：US20240071990A1

公开(公告)日：2024-02-29

申请号：US17896030

申请日：2022-08-25

Applicant: Micron Technology, Inc.

Inventor： Kelvin Tan Aik Boo ,  Seng Kim Ye ,  Hong Wan Ng ,  Ling Pan ,  See Hiong Leow

IPC: H01L23/00 ,  H01L21/48 ,  H01L23/498

CPC classification number: H01L24/81 ,  H01L21/4846 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/13082 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/13169 ,  H01L2224/13173 ,  H01L2224/13176 ,  H01L2224/13178 ,  H01L2224/1318 ,  H01L2224/13181 ,  H01L2224/13183 ,  H01L2224/13184 ,  H01L2224/16238 ,  H01L2224/81385 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81466 ,  H01L2224/81469 ,  H01L2224/81473 ,  H01L2224/81476 ,  H01L2224/81478 ,  H01L2224/8148 ,  H01L2224/81481 ,  H01L2224/81483 ,  H01L2224/81484 ,  H01L2224/81815 ,  H01L2924/3841

Abstract: A semiconductor device assembly including a semiconductor device having a plurality of pillars disposed on a backside surface of the semiconductor device; and a substrate, including: a solder mask layer disposed on a front side surface of the substrate, a plurality of extended bond pads disposed on the frontside surface of the substrate and surrounded by the solder mask layer, the plurality of extended bond pads each having a top surface higher than a top surface of the solder mask layer, and wherein the semiconductor device is directly attached to the substrate by bonding each of the plurality of pillars of the semiconductor device to the top surface of a corresponding one of the plurality of extended bond pads with a solder connection.