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    BUS INTERFACE SYSTEM
    11.
    发明申请
    BUS INTERFACE SYSTEM 审中-公开
    总线接口系统

    公开(公告)号：US20150169482A1

    公开(公告)日：2015-06-18

    申请号：US14575491

    申请日：2014-12-18

    Applicant: RF MICRO DEVICES, INC.

    Inventor： Christopher Truong Ngo ,  Alexander Wayne Hietala ,  Christian Rye Iversen ,  Ruediger Bauder

    IPC: G06F13/362 ,  G06F1/08

    CPC classification number: G06F13/3625 ,  G06F13/4278 ,  Y02D10/14 ,  Y02D10/151

    Abstract: A bus interface system is disclosed that includes a master bus controller and a slave bus controller that are coupled by a bus line. The slave bus controller includes a decoder that allows for data to be transmitted along just the bus line. The decoder includes an oscillator, a first counter, and a comparison circuit. The oscillator is configured to be enabled by data pulses defined by the input data signal and generate oscillation pulses while enabled. The first counts the oscillation pulses and indicates a number of the oscillation pulses generated during a time slot. The comparison circuit is configured to this number with a reference number and generate a data output that represents a first logical value in response to the number being greater than the reference parameter and represents a second logical value in response to the number being less than the reference parameter.

    Abstract translation: 公开了一种总线接口系统，其包括通过总线耦合的主总线控制器和从总线控制器。 从总线控制器包括允许数据沿着总线传输的解码器。 解码器包括振荡器，第一计数器和比较电路。 振荡器被配置为通过由输入数据信号定义的数据脉冲使能，并在使能时产生振荡脉冲。 第一个对振荡脉冲进行计数，并指示在时隙期间产生的振荡脉冲的数量。 比较电路被配置为具有参考号的该号码，并且响应于该数量大于参考参数而生成表示第一逻辑值的数据输出，并且响应于小于参考的数字表示第二逻辑值 参数。

    Average frequency control of switcher for envelope tracking
    12.
    发明授权
    Average frequency control of switcher for envelope tracking 有权
    用于包络跟踪的切换器的平均频率控制

    公开(公告)号：US09294041B2

    公开(公告)日：2016-03-22

    申请号：US13661164

    申请日：2012-10-26

    Applicant: RF Micro Devices, Inc.

    Inventor： Nadim Khlat ,  Christopher Truong Ngo

    IPC: H03F1/30 ,  H03F1/02 ,  H03F3/19 ,  H02M3/156

    CPC classification number: H03F1/0227 ,  H02M3/156 ,  H03F3/19 ,  H03F2200/108 ,  H03F2200/351

    Abstract: This disclosure relates generally to radio frequency (RF) switching converters and RF amplification devices that use RF switching converters. For example, an RF switching converter may include a switching circuit that receives a power source voltage and a switching controller that receives a target average frequency value identifying a target average frequency. The switching circuit is switchable so as to generate a pulsed output voltage from the power source voltage. The switching controller switches the switching circuit such that the pulsed output voltage has an average pulse frequency. The switching controller also detects that the average pulse frequency of the pulsed output voltage during a time period differs from the target average frequency, and reduces a difference between the average pulse frequency and the target average frequency. In this manner, the effects of manufacturing variations and operational variations on the average pulse frequency can be eliminated, or at least diminished.

    Abstract translation: 本公开一般涉及使用RF开关转换器的射频（RF）开关转换器和RF放大器件。 例如，RF开关转换器可以包括接收电源电压的开关电路和接收识别目标平均频率的目标平均频率值的开关控制器。 开关电路是可切换的，以便从电源电压产生脉冲输出电压。 开关控制器切换开关电路，使得脉冲输出电压具有平均脉冲频率。 切换控制器还检测在一段时间内脉冲输出电压的平均脉冲频率与目标平均频率不同，并且减小了平均脉冲频率和目标平均频率之间的差。 以这种方式，可以消除或至少减少制造变化和操作变化对平均脉冲频率的影响。

    CLOCK AND DATA RECOVERY USING DUAL MANCHESTER ENCODED DATA STREAMS
    13.
    发明申请
    CLOCK AND DATA RECOVERY USING DUAL MANCHESTER ENCODED DATA STREAMS 有权
    使用双重编码数据流的时钟和数据恢复

    公开(公告)号：US20150023458A1

    公开(公告)日：2015-01-22

    申请号：US14334978

    申请日：2014-07-18

    Applicant: RF Micro Devices, Inc.

    Inventor： Christopher Truong Ngo

    IPC: H04L25/49

    CPC classification number: H04L25/4904 ,  H04L25/14

    Abstract: Two Manchester encoded bit streams each bit stream with accompanying embedded clock data are disclosed. The two encoded bit streams are encoded at the source using opposite polarities of the source clock to position transitions within the bit streams at the rising and falling edges of the source clock. The receiver may extract the clock data from both bit streams. Because both rising and falling edge clock data is available between the two bit streams, the receiver does not need a phase locked loop (PLL) or incur the accompanying expense of such PLL. Further, by avoiding use of a PLL, a nearly all digital circuit may be created, which may provide further cost and space savings. Still further, a higher data throughput is provided without increasing pin count or signal bandwidth.

    Abstract translation: 公开了两个曼彻斯特编码比特流，每个比特流与伴随的嵌入式时钟数据。 使用源时钟的相反极性在源处对两个编码比特流进行编码，以在源时钟的上升沿和下降沿定位位流内的转换。 接收机可以从两个比特流中提取时钟数据。 因为两个比特流之间的上升沿和下降沿时钟数据都可用，所以接收机不需要锁相环（PLL）或者产生这种PLL的伴随费用。 此外，通过避免使用PLL，可以创建几乎所有的数字电路，这可以提供进一步的成本和空间节省。 此外，提供更高的数据吞吐量而不增加引脚数或信号带宽。

    EXTRACTING CLOCK INFORMATION FROM A SERIAL COMMUNICATIONS BUS FOR USE IN RF COMMUNICATIONS CIRCUITRY
    14.
    发明申请
    EXTRACTING CLOCK INFORMATION FROM A SERIAL COMMUNICATIONS BUS FOR USE IN RF COMMUNICATIONS CIRCUITRY 有权
    从RF通信电路中使用的串行通信总线提取时钟信息

    公开(公告)号：US20130294554A1

    公开(公告)日：2013-11-07

    申请号：US13937307

    申请日：2013-07-09

    Applicant: RF Micro Devices, Inc.

    Inventor： Dharma Reddy Kadam ,  Christopher Truong Ngo ,  Nadim Khlat

    IPC: H04L7/04

    CPC classification number: H04L7/04 ,  G06F13/385 ,  H04J3/0685

    Abstract: The present disclosure relates to RF front-end (RFFE) circuitry that includes multiple RFFE circuits, each of which may be provided by a separate integrated circuit (IC), front-end module, or both. As such, the RFFE circuits may be connected to one another using an RFFE serial communications bus. Further, one or more of the RFFE circuits may need an accurate clock source for analog-to-digital conversion (ADC), digital-to-analog conversion (DAC), calibration, sensor measurements, or the like. Instead of including an integral clock source circuit or receiving a separate external clock signal, an RFFE circuit may extract clock information from the RFFE serial communications bus to provide one or more clock signals. The clock information may be associated with one or more serial communications commands via the RFFE serial communications bus, may be associated with alternate functionality of the RFFE serial communications bus, or both.

    Abstract translation: 本公开涉及包括多个RFFE电路的RF前端（RFFE）电路，每个RFFE电路可以由单独的集成电路（IC），前端模块或两者提供。 因此，RFFE电路可以使用RFFE串行通信总线彼此连接。 此外，一个或多个RFFE电路可能需要用于模数转换（ADC），数模转换（DAC），校准，传感器测量等的精确时钟源。 RFFE电路不是包含集成时钟源电路或者接收单独的外部时钟信号，而是可以从RFFE串行通信总线提取时钟信息以提供一个或多个时钟信号。 时钟信息可以经由RFFE串行通信总线与一个或多个串行通信命令相关联，可以与RFFE串行通信总线或两者的备用功能相关联。

    GROUP WRITE TECHNIQUE FOR A BUS INTERFACE SYSTEM
    16.
    发明申请
    GROUP WRITE TECHNIQUE FOR A BUS INTERFACE SYSTEM 审中-公开
    用于总线接口系统的组写入技术

    公开(公告)号：US20150193321A1

    公开(公告)日：2015-07-09

    申请号：US14659379

    申请日：2015-03-16

    Applicant: RF Micro Devices, Inc.

    Inventor： Christopher Truong Ngo ,  Alexander Wayne Hietala

    IPC: G06F11/30 ,  G06F11/16 ,  G06F11/22 ,  G06F11/10

    CPC classification number: G06F11/3027 ,  G06F1/10 ,  G06F1/26 ,  G06F11/1004 ,  G06F11/1052 ,  G06F11/1604 ,  G06F11/221

    Abstract: Embodiments of bus interface systems and methods of operating the same are disclosed. In one embodiment, a bus interface system includes a master bus controller and multiple slave bus controllers that are each coupled to a bus line. The master bus controller is configured to generate a first set of data pulses along the bus line representing a payload segment. Each of the slave bus controllers decodes the first set of data pulses along the bus line representing the payload segment and performs an error check. Each slave bus controller is then configured to generate an acknowledgement pulse along the bus line to indicate that the slave bus controller's particular error check was passed. In this manner, the bus interface system can perform a group write bus function and the master bus controller can determine that the multiple slave bus controllers each received an accurate copy of the payload segment.

    Abstract translation: 公开了总线接口系统的实施例及其操作方法。 在一个实施例中，总线接口系统包括主总线控制器和多个从总线控制器，每个从总线控制器耦合到总线。 主总线控制器被配置为沿着表示有效载荷段的总线产生第一组数据脉冲。 每个从总线控制器沿着表示有效载荷段的总线解码第一组数据脉冲，并执行错误检查。 然后，每个从总线控制器被配置为沿着总线生成确认脉冲，以指示从总线控制器的特定错误检查已经通过。 以这种方式，总线接口系统可以执行组写总线功能，并且主总线控制器可以确定多个从总线控制器各自接收到有效载荷段的准确副本。

    Clock and data recovery using dual manchester encoded data streams
    18.
    发明授权
    Clock and data recovery using dual manchester encoded data streams 有权
    使用双曼彻斯特编码数据流的时钟和数据恢复

    公开(公告)号：US09054941B2

    公开(公告)日：2015-06-09

    申请号：US14334978

    申请日：2014-07-18

    Applicant: RF Micro Devices, Inc.

    Inventor： Christopher Truong Ngo

    IPC: H04L5/16 ,  H04L25/49

    CPC classification number: H04L25/4904 ,  H04L25/14

    Abstract: Two Manchester encoded bit streams each bit stream with accompanying embedded clock data are disclosed. The two encoded bit streams are encoded at the source using opposite polarities of the source clock to position transitions within the bit streams at the rising and falling edges of the source clock. The receiver may extract the clock data from both bit streams. Because both rising and falling edge clock data is available between the two bit streams, the receiver does not need a phase locked loop (PLL) or incur the accompanying expense of such PLL. Further, by avoiding use of a PLL, a nearly all digital circuit may be created, which may provide further cost and space savings. Still further, a higher data throughput is provided without increasing pin count or signal bandwidth.

    Abstract translation: 公开了两个曼彻斯特编码比特流，每个比特流与伴随的嵌入式时钟数据。 使用源时钟的相反极性在源处对两个编码比特流进行编码，以在源时钟的上升沿和下降沿定位位流内的转换。 接收机可以从两个比特流中提取时钟数据。 因为两个比特流之间的上升沿和下降沿时钟数据都可用，所以接收机不需要锁相环（PLL）或者产生这种PLL的伴随费用。 此外，通过避免使用PLL，可以创建几乎所有的数字电路，这可以提供进一步的成本和空间节省。 此外，提供更高的数据吞吐量而不增加引脚数或信号带宽。

    Extracting clock information from a serial communications bus for use in RF communications circuitry
    19.
    发明授权
    Extracting clock information from a serial communications bus for use in RF communications circuitry 有权
    从串行通信总线提取时钟信息，用于RF通信电路

    公开(公告)号：US08774735B2

    公开(公告)日：2014-07-08

    申请号：US13937307

    申请日：2013-07-09

    Applicant: RF Micro Devices, Inc.

    Inventor： Dharma Reddy Kadam ,  Christopher Truong Ngo ,  Nadim Khlat

    IPC: H04B1/02

    CPC classification number: H04L7/04 ,  G06F13/385 ,  H04J3/0685

    Abstract: The present disclosure relates to RF front-end (RFFE) circuitry that includes multiple RFFE circuits, each of which may be provided by a separate integrated circuit (IC), front-end module, or both. As such, the RFFE circuits may be connected to one another using an RFFE serial communications bus. Further, one or more of the RFFE circuits may need an accurate clock source for analog-to-digital conversion (ADC), digital-to-analog conversion (DAC), calibration, sensor measurements, or the like. Instead of including an integral clock source circuit or receiving a separate external clock signal, an RFFE circuit may extract clock information from the RFFE serial communications bus to provide one or more clock signals. The clock information may be associated with one or more serial communications commands via the RFFE serial communications bus, may be associated with alternate functionality of the RFFE serial communications bus, or both.

    Abstract translation: 本公开涉及包括多个RFFE电路的RF前端（RFFE）电路，每个RFFE电路可以由单独的集成电路（IC），前端模块或两者提供。 因此，RFFE电路可以使用RFFE串行通信总线彼此连接。 此外，一个或多个RFFE电路可能需要用于模数转换（ADC），数模转换（DAC），校准，传感器测量等的精确时钟源。 RFFE电路不是包含集成时钟源电路或者接收单独的外部时钟信号，而是可以从RFFE串行通信总线提取时钟信息以提供一个或多个时钟信号。 时钟信息可以经由RFFE串行通信总线与一个或多个串行通信命令相关联，可以与RFFE串行通信总线或两者的备用功能相关联。

    OPEN LOOP RIPPLE CANCELLATION CIRCUIT IN A DC-DC CONVERTER
    20.
    发明申请
    OPEN LOOP RIPPLE CANCELLATION CIRCUIT IN A DC-DC CONVERTER 有权
    DC-DC转换器中的开环纹波消除电路

    公开(公告)号：US20140077787A1

    公开(公告)日：2014-03-20

    申请号：US14027416

    申请日：2013-09-16

    Applicant: RF Micro Devices, Inc.

    Inventor： Philippe Gorisse ,  Nadim Khlat ,  Christopher Truong Ngo

    IPC: H02M1/14

    CPC classification number: H02M1/14 ,  H02M1/15 ,  H02M2001/0045 ,  H03F1/0211 ,  H03F1/0261

    Abstract: A direct current (DC)-DC converter, which includes an open loop ripple cancellation circuit, a switching supply, and a parallel amplifier, is disclosed. During a calibration mode, the parallel amplifier provides a parallel amplifier output current to regulate a power supply output voltage based on a calibration setpoint. The switching supply drives the parallel amplifier output current toward zero using a switching control signal, such that during the calibration mode, an estimate of a current gain is based on the switching control signal. Further, during the calibration mode, the open loop ripple cancellation circuit is disabled. During a normal operation mode, the open loop ripple cancellation circuit provides a ripple cancellation current, which is based on the estimate of the current gain.

    Abstract translation: 公开了一种直流（DC）-DC转换器，其包括开环纹波消除电路，开关电源和并联放大器。 在校准模式期间，并行放大器提供并行放大器输出电流，以调节基于校准设定值的电源输出电压。 开关电源使用开关控制信号将平行放大器输出电流驱动到零，使得在校准模式期间，电流增益的估计基于开关控制信号。 此外，在校准模式期间，开环纹波消除电路被禁用。 在正常工作模式下，开环纹波消除电路提供纹波消除电流，其基于当前增益的估计。

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