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    Semiconductor device
    11.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US12166132B2

    公开(公告)日：2024-12-10

    申请号：US17690371

    申请日：2022-03-09

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Minhee Cho ,  Mintae Ryu ,  Sungwon Yoo ,  Wonsok Lee ,  Hyunmog Park ,  Kiseok Lee

    IPC: H01L29/786

    Abstract: A semiconductor device including a conductive line on a substrate, a first gate electrode on the conductive line, a second gate electrode separated by a gate isolation insulating layer on the first gate electrode, a first channel layer on a side surface of the first gate electrode, with a first gate insulating layer therebetween, a first source/drain region on another side surface of the first gate electrode, a second channel layer on another side surface of the second gate electrode on a side that is opposite to the first channel layer, with a second gate insulating layer therebetween, a second source/drain region on the second channel layer, and a third source/drain region on the first channel layer and on a side surface of the second gate electrode on a same side as the first channel layer may be provided.

    SEMICONDUCTOR DEVICES HAVING HYBRID CAPACITORS AND METHODS FOR FABRICATING THE SAME
    16.
    发明申请
    SEMICONDUCTOR DEVICES HAVING HYBRID CAPACITORS AND METHODS FOR FABRICATING THE SAME 审中-公开
    具有混合电容器的半导体器件及其制造方法

    公开(公告)号：US20150236084A1

    公开(公告)日：2015-08-20

    申请号：US14703933

    申请日：2015-05-05

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Dongkyun Park ,  Han-Young Kim ,  Joon Kim ,  Hyun Park ,  Junghwan Oh ,  Minhee Cho

    IPC: H01L49/02 ,  H01L21/311 ,  H01L21/285

    CPC classification number: H01L28/91 ,  H01L21/28562 ,  H01L21/31116 ,  H01L27/10852

    Abstract: A semiconductor device includes a plurality of capacitors disposed on a substrate and a support pattern supporting upper portions and lower portions of the capacitors. Each of the capacitors includes a lower electrode, an upper electrode, and a dielectric layer between the lower and upper electrodes. The lower electrode includes a first electrode portion electrically connected to the substrate and having a solid shape and a second electrode portion stacked on the first electrode portion and having a shape comprising an opening therein. The support pattern includes an upper pattern contacting sidewalls of top end portions of the lower electrodes and a lower pattern vertically spaced apart from the upper pattern. The lower pattern contacts sidewalls under the top end portions of the lower electrodes.

    Abstract translation: 半导体器件包括设置在基板上的多个电容器和支撑电容器的上部和下部的支撑图案。 每个电容器包括在下电极和上电极之间的下电极，上电极和电介质层。 下电极包括电连接到基板并具有固体形状的第一电极部分和堆叠在第一电极部分上并具有包括其中的开口的形状的第二电极部分。 支撑图案包括接触下部电极的顶端部的侧壁的上部图案和与上部图案垂直间隔开的下部图案。 下部图案接触下部电极的顶端部分的侧壁。

    SEMICONDUCTOR DEVICES
    17.
    发明公开
    SEMICONDUCTOR DEVICES 审中-公开

    公开(公告)号：US20240030342A1

    公开(公告)日：2024-01-25

    申请号：US18141060

    申请日：2023-04-28

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sanghoon Uhm ,  Minhee Cho

    IPC: H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H01L21/768 ,  H01L29/786

    CPC classification number: H01L29/7827 ,  H01L29/7889 ,  H01L29/7926 ,  H01L21/76829 ,  H01L29/78693

    Abstract: A semiconductor device includes bit lines, gate electrodes, a gate insulation pattern and a channel structure on a substrate. Each of the bit lines extends in a first direction, and the bit lines may be spaced apart from each other in a second direction. The gate electrodes are spaced apart from each other in the first direction, and each of the gate electrodes extends in the second direction.
    For each of the gate electrodes, a gate insulation pattern is formed on a sidewall in the first direction of the gate electrode, and a channel structure is formed on a sidewall in the first direction of the gate insulation pattern. The channel structure includes a first amorphous channel including an amorphous oxide semiconductor and a first crystalline channel including a crystalline oxide semiconductor and contacting an upper surface of the first amorphous channel.

    SEMICONDUCTOR MEMORY DEVICE
    19.
    发明公开
    SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20230292490A1

    公开(公告)日：2023-09-14

    申请号：US18081905

    申请日：2022-12-15

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yongjin Lee ,  Yongseok Kim ,  Mintae Ryu ,  Huije Ryu ,  Sungwon Yoo ,  Wonsok Lee ,  Minhee Cho

    IPC: H10B12/00

    CPC classification number: H10B12/315 ,  H10B12/482

    Abstract: A semiconductor memory device includes a substrate, a conductive line extending in a first horizontal direction above the substrate, an isolation insulating layer including a channel trench extending in a second horizontal direction intersecting with the first horizontal direction and extending from an upper surface to a lower surface of the isolation insulating layer, above the conductive line, a channel structure disposed above the conductive line, a gate electrode extending in the second horizontal direction, in the channel trench, a capacitor structure above the isolation insulating layer, and a contact structure interposed between the channel structure and the capacitor structure, wherein the channel structure includes an amorphous oxide semiconductor layer disposed in the channel trench above the conductive line, and an upper crystalline oxide semiconductor layer interposed between the amorphous oxide semiconductor layer and the contact structure.

    Memory device
    20.
    发明授权
    Memory device 有权

    公开(公告)号：US11482267B2

    公开(公告)日：2022-10-25

    申请号：US17330828

    申请日：2021-05-26

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Minhee Cho ,  Woobin Song ,  Hyunmog Park ,  Sangkil Lee

    IPC: G11C11/00 ,  H01L27/1159 ,  H01L27/108 ,  G11C11/4096 ,  G11C11/22 ,  H01L27/11592

    Abstract: A memory device includes a substrate including first and second regions, the first region having first wordlines and first bitlines, and the second region having second wordlines and second bitlines, a first memory cell array including first memory cells in the first region, the first memory cell array having volatility, and each of the first memory cells including a cell switch having a first channel region adjacent to a corresponding first wordline of the first wordlines, and a capacitor connected to the cell switch, and a second memory cell array including second memory cells in the second region, the second memory cell array having non-volatility, and each of the second memory cells including a second channel region adjacent to a corresponding second wordline of the second wordlines, and a ferroelectric layer between the corresponding second wordline of the second wordlines and the second channel region.

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