公开(公告)号：US20210111104A1

公开(公告)日：2021-04-15

申请号：US16677103

申请日：2019-11-07

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Inpil YOO ,  Seungwon IM ,  JooYang EOM ,  Jerome TEYSSEYRE

IPC: H01L23/495 ,  H01L23/00

Abstract: Implementations of a clip may include a first copper layer directly bonded to a first side of a ceramic layer, a second copper layer directly bonded to a second side of the ceramic layer, the second side of the ceramic layer opposite the first side of the ceramic layer, and a plurality of channels partially etched into a thickness of the second copper layer.

公开(公告)号：US20230019930A1

公开(公告)日：2023-01-19

申请号：US17806961

申请日：2022-06-15

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Inpil YOO ,  Jerome TEYSSEYRE ,  Oseob JEON ,  Keunhyuk LEE ,  Michael J. SEDDON

IPC: H01L23/44 ,  H05K7/20

Abstract: Implementations of a semiconductor package may include one or more power semiconductor die included in a die module; a first heat sink directly coupled to one or more source pads of the die module; a second heat sink directly coupled to one or more drain pads of the die module; a gate contact coupled with one or more gate pads of the die module; and a coating coupled directly to the die module. The gate contact may be configured to extend through an immersion cooling enclosure.

公开(公告)号：US20220406744A1

公开(公告)日：2022-12-22

申请号：US17664749

申请日：2022-05-24

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Jooyang EOM ,  Seungwon IM ,  Maria Cristina ESTACIO ,  Jerome TEYSSEYRE ,  Inpil YOO

IPC: H01L23/00 ,  H01L23/373

Abstract: Implementations of semiconductor devices may include a die coupled over a lead frame, a redistribution layer (RDL) coupled over the die, a first plurality of vias coupled between the RDL and the die, and a second plurality of vias coupled over and directly to the lead frame. The second plurality of vias may be adjacent to an outer edge of the semiconductor device and may be electrically isolated from the die.

公开(公告)号：US20220157801A1

公开(公告)日：2022-05-19

申请号：US16949896

申请日：2020-11-19

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Jerome TEYSSEYRE ,  Inpil YOO ,  JooYang EOM

IPC: H01L25/00 ,  H01L25/18 ,  H01L25/07 ,  H01L23/467 ,  H01L23/473 ,  H01L23/367

Abstract: According to an aspect, a power module package includes a plurality of power modules including a first power module and a second power module, a plurality of heat sinks including a first heat sink coupled to the first power module and a second heat sink coupled to the second power module, and a module carrier coupled to the plurality of power modules, where the module carrier includes a first region defining a first heat-sink slot and a second region defining a second heat-sink slot. The first heat sink extends at least partially through the first heat-sink slot and the second heat sink extends at least partially through the second heat-sink slot. The power module package includes a housing coupled to the module carrier and a ring member located between the module carrier and the housing.