公开(公告)号：US20240395662A1

公开(公告)日：2024-11-28

申请号：US18324362

申请日：2023-05-26

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Ingoo KANG ,  Oseob JEON ,  Seungwon IM

IPC: H01L23/473 ,  H01L21/48 ,  H01L25/07

Abstract: A package includes a semiconductor die disposed on a three-layer substrate. The three-layer substrate includes a ceramic layer disposed between a top metal layer and a bottom metal layer. The semiconductor die is disposed on the top metal layer. An array of mesas is defined in the bottom metal layer with grooves between the mesas forming a path for cooling fluid flow across a surface of the bottom metal layer.

公开(公告)号：US20240282663A1

公开(公告)日：2024-08-22

申请号：US18635186

申请日：2024-04-15

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Seungwon IM ,  Dongwook KANG ,  Oseob JEON

IPC: H01L23/373 ,  H01L23/31 ,  H01L23/367 ,  H01L23/473 ,  H01L25/07

CPC classification number: H01L23/3735 ,  H01L23/3107 ,  H01L23/3672 ,  H01L23/473 ,  H01L25/072

Abstract: In a general aspect, an electronic device assembly can include a semiconductor device assembly including a ceramic substrate; a patterned metal layer disposed on a first surface of the ceramic substrate; and a semiconductor die disposed on the patterned metal layer. The electronic device assembly can also include a thermal dissipation appliance. Ceramic material of a second surface of the ceramic substrate can be direct-bonded to a surface of the thermal dissipation appliance. The second surface of the ceramic substrate can be opposite the first surface of the ceramic substrate.

公开(公告)号：US20240186211A1

公开(公告)日：2024-06-06

申请号：US18441484

申请日：2024-02-14

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Jooyang EOM ,  Inpil YOO ,  Seungwon IM ,  Byoungok LEE

IPC: H01L23/367 ,  H01L21/48

CPC classification number: H01L23/3672 ,  H01L21/4882

Abstract: In a general aspect, an apparatus includes a substrate and a metal layer disposed on a surface of the substrate. The apparatus also includes a first recess and a second recess formed in the metal layer, and a folded cooling fin. A first portion of the folded cooling fin is disposed within the first recess and coupled with the metal layer, and a second portion of the folded cooling fin is disposed in the second recess and coupled with the metal layer.

公开(公告)号：US20240162110A1

公开(公告)日：2024-05-16

申请号：US18054229

申请日：2022-11-10

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Seungwon IM ,  Jeungdae KIM ,  Oseob JEON ,  Byoungok LEE

IPC: H01L23/373 ,  H01L21/56 ,  H01L23/31 ,  H01L23/42 ,  H01L23/495

CPC classification number: H01L23/3735 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/42 ,  H01L23/49503 ,  H01L24/32 ,  H01L2224/32245

Abstract: In a general aspect, a semiconductor device package can include a die attach paddle having a first surface and a second surface that is opposite the first surface; a semiconductor die coupled with the first surface of the die attach paddle, and a direct-bonded-metal (DBM) substrate The DBM substrate can include a ceramic layer having a first surface and a second surface that is opposite the first surface, a first metal layer disposed on the first surface of the ceramic layer and coupled with the second surface of the die attach paddle, a second metal layer disposed on the second surface of the ceramic layer, and a thermally conductive adhesive disposed on the second metal layer, At least a surface of the thermally conductive adhesive can be exposed external to the device package. The thermally conductive adhesive can be configured for coupling the device package with a thermal dissipation appliance.

公开(公告)号：US20240120253A1

公开(公告)日：2024-04-11

申请号：US18182552

申请日：2023-03-13

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Oseob JEON ,  Dongwook KANG ,  Seungwon IM ,  Jihwan KIM

IPC: H01L23/373 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/367 ,  H01L23/495

CPC classification number: H01L23/373 ,  H01L21/4846 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/3672 ,  H01L23/49568 ,  H01L24/32 ,  H01L2224/32245

Abstract: An integrated substrate may include a conductor layer; a heat sink including a plurality of fins extending therefrom; and a dielectric layer including boron nitride chemically bonded to the conductor layer and to the heat sink with an epoxy.

公开(公告)号：US20230361011A1

公开(公告)日：2023-11-09

申请号：US18308467

申请日：2023-04-27

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Seungwon IM ,  Oseob JEON

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/433

CPC classification number: H01L23/49811 ,  H01L23/3121 ,  H01L23/4334

Abstract: In a general aspect, an electronic device assembly includes a substrate having a surface, a patterned metal layer disposed on the surface of the substrate, a semiconductor device circuit implemented on the patterned metal layer, and a molded body including a plurality of signal pin. A signal pin of the plurality of signal pins includes a first portion extending out of a first surface of the molded body. The first portion is externally accessible. The signal pin of the plurality of signal pins also includes a second portion extending out of a second surface of the molded body opposite the first surface. The second portion of the signal pin of the plurality of signal pins include is internal to the electronic device assembly, is electrically coupled with the patterned metal layer, and is electrically continuous with the first portion.

公开(公告)号：US20220199602A1

公开(公告)日：2022-06-23

申请号：US17247797

申请日：2020-12-23

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Jonghwan BAEK ,  JeongHyuk PARK ,  Seungwon IM ,  Keunhyuk LEE

IPC: H01L25/18 ,  H01L23/495 ,  H01L23/367 ,  H01L23/31 ,  H01L23/00 ,  H01L25/00

Abstract: Described implementations provide wireless, surface mounting of at least two semiconductor die on die attach pads (DAPs) of the semiconductor package, where the at least two semiconductor die are electrically connected by a clip. A stress buffer layer may be provided on the clip, and a heatsink may be provided on the stress buffer layer. The heatsink may be secured with an external mold material.

公开(公告)号：US20210066256A1

公开(公告)日：2021-03-04

申请号：US16671450

申请日：2019-11-01

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Seungwon IM ,  ByoungOk LEE ,  Oseob JEON

IPC: H01L25/07 ,  H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56

Abstract: In a general aspect, a semiconductor device can include a substrate and a positive power supply terminal electrically coupled with the substrate, the positive power supply terminal being arranged in a first plane. The device can also include a first negative power supply terminal, laterally disposed from the positive power supply terminal and arranged in the first plane. The device can further include a second negative power supply terminal, laterally disposed from the positive power supply terminal and arranged in the first plane. The positive power supply terminal can be disposed between the first and second negative power supply terminals. The device can also include a conductive clip electrically coupling the first negative power supply terminal with the second negative power supply terminal via a conductive bridge. A portion of the conductive bridge can be arranged in a second plane that is parallel to, and non-coplanar with the first plane.

公开(公告)号：US20180315681A1

公开(公告)日：2018-11-01

申请号：US15714539

申请日：2017-09-25

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Seungwon IM ,  Oseob JEON ,  Byoungok LEE ,  Yoonsoo LEE ,  Joonseo SON ,  Dukyong LEE ,  Changyoung PARK

IPC: H01L23/433 ,  H01L23/24 ,  H01L25/065 ,  H01L23/498 ,  H01L23/13

Abstract: Implementations of semiconductor packages may include a first substrate coupled to a first die, a second substrate coupled to a second die, and a spacer included within a perimeter of the first substrate and within a perimeter of a second substrate, the spacer coupled between the first die and the second die, the spacer include a junction cooling pipe therethrough.

公开(公告)号：US20250125297A1

公开(公告)日：2025-04-17

申请号：US18999120

申请日：2024-12-23

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Maria Cristina ESTACIO ,  Jooyang EOM ,  Jerome TEYSSEYRE ,  Inpil YOO ,  Seungwon IM

IPC: H01L23/00 ,  H01L23/373 ,  H01L23/495 ,  H01L25/07

Abstract: Implementations of semiconductor devices may include a die coupled over a lead frame, a redistribution layer (RDL) coupled over the die, a first plurality of vias coupled between the RDL and the die, and a second plurality of vias coupled over and directly to the lead frame. The second plurality of vias may be adjacent to an outer edge of the semiconductor device and may be electrically isolated from the die.