公开(公告)号：US20220157801A1

公开(公告)日：2022-05-19

申请号：US16949896

申请日：2020-11-19

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Jerome TEYSSEYRE ,  Inpil YOO ,  JooYang EOM

IPC: H01L25/00 ,  H01L25/18 ,  H01L25/07 ,  H01L23/467 ,  H01L23/473 ,  H01L23/367

Abstract: According to an aspect, a power module package includes a plurality of power modules including a first power module and a second power module, a plurality of heat sinks including a first heat sink coupled to the first power module and a second heat sink coupled to the second power module, and a module carrier coupled to the plurality of power modules, where the module carrier includes a first region defining a first heat-sink slot and a second region defining a second heat-sink slot. The first heat sink extends at least partially through the first heat-sink slot and the second heat sink extends at least partially through the second heat-sink slot. The power module package includes a housing coupled to the module carrier and a ring member located between the module carrier and the housing.

公开(公告)号：US20220173022A1

公开(公告)日：2022-06-02

申请号：US17651621

申请日：2022-02-18

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Inpil YOO ,  Seungwon IM ,  JooYang EOM ,  Jerome TEYSSEYRE

IPC: H01L23/495 ,  H01L23/00

Abstract: Implementations of a clip may include a first copper layer directly bonded to a first side of a ceramic layer, a second copper layer directly bonded to a second side of the ceramic layer, the second side of the ceramic layer opposite the first side of the ceramic layer, and a plurality of channels partially etched into a thickness of the second copper layer.

公开(公告)号：US20220157688A1

公开(公告)日：2022-05-19

申请号：US16949894

申请日：2020-11-19

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： JooYang EOM ,  Inpil YOO ,  Seungwon IM ,  ByoungOk LEE

IPC: H01L23/367 ,  H01L21/48

Abstract: In a general aspect, an apparatus can include a metal layer disposed on a surface of the substrate. The apparatus can also include a recess formed in the metal layer and a cooling fin coupled with the metal layer. A portion of the cooling fin can be disposed within the recess.

公开(公告)号：US20230253362A1

公开(公告)日：2023-08-10

申请号：US17650265

申请日：2022-02-08

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Seungwon IM ,  JooYang EOM ,  Inpil YOO ,  Oseob JEON

IPC: H01L23/00 ,  H01L23/495 ,  H01L25/065

CPC classification number: H01L24/83 ,  H01L24/32 ,  H01L24/33 ,  H01L23/49568 ,  H01L25/0655 ,  H01L23/49575 ,  H01L2224/8334 ,  H01L2224/33181 ,  H01L2224/32245

Abstract: A method includes disposing a first direct bonded metal (DBM) substrate substantially parallel to a second DBM substrate a distance apart to enclose a space. The method further includes disposing at least a semiconductor die in the space, and bonding the semiconductor die to the first DBM substrate using a first adhesive layer without an intervening spacer block between the semiconductor die and the first DBM substrate, and bonding the semiconductor die to the second DBM substrate using a second adhesive without an intervening spacer block between the semiconductor die and the second DBM substrate.

公开(公告)号：US20210242167A1

公开(公告)日：2021-08-05

申请号：US17158143

申请日：2021-01-26

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Inpil YOO ,  Maria Cristina ESTACIO ,  Jerome TEYSSEYRE ,  Seungwon IM ,  JooYang EOM

IPC: H01L23/00 ,  H01L23/495 ,  H01L23/52 ,  H01L21/56

Abstract: Implementations of a semiconductor package may include two or more die, each of the two more die coupled to a metal layer at a drain of each of the two more die, the two or more die and each metal layer arranged in two parallel planes; a first interconnect layer coupled at a source of each of the two more die; a second interconnect layer coupled to a gate of each of the two or more die and to a gate package contact through one or more vias; and an encapsulant that encapsulates the two or more die and at least a portion of the first interconnect layer, each metal layer, and the second interconnect layer.

公开(公告)号：US20240258268A1

公开(公告)日：2024-08-01

申请号：US18632548

申请日：2024-04-11

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Inpil YOO ,  Maria Cristina ESTACIO ,  Jerome TEYSSEYRE ,  Seungwon IM ,  JooYang EOM

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L23/495 ,  H01L23/52

CPC classification number: H01L24/92 ,  H01L21/56 ,  H01L23/49527 ,  H01L23/49575 ,  H01L23/52 ,  H01L24/24 ,  H01L24/29 ,  H01L24/32 ,  H01L24/40 ,  H01L24/73 ,  H01L24/82 ,  H01L24/83 ,  H01L24/84 ,  H01L23/3107 ,  H01L23/49513 ,  H01L2224/24011 ,  H01L2224/24101 ,  H01L2224/24105 ,  H01L2224/24137 ,  H01L2224/24246 ,  H01L2224/29139 ,  H01L2224/32245 ,  H01L2224/40101 ,  H01L2224/40137 ,  H01L2224/73213 ,  H01L2224/73217 ,  H01L2224/73263 ,  H01L2224/73267 ,  H01L2224/82101 ,  H01L2224/8384 ,  H01L2224/8484 ,  H01L2224/92142 ,  H01L2224/92144

Abstract: Implementations of a semiconductor package may include two or more die, each of the two more die coupled to a metal layer at a drain of each of the two more die, the two or more die and each metal layer arranged in two parallel planes; a first interconnect layer coupled at a source of each of the two more die; a second interconnect layer coupled to a gate of each of the two or more die and to a gate package contact through one or more vias; and an encapsulant that encapsulates the two or more die and at least a portion of the first interconnect layer, each metal layer, and the second interconnect layer.

公开(公告)号：US20220406767A1

公开(公告)日：2022-12-22

申请号：US17822844

申请日：2022-08-29

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Jerome TEYSSEYRE ,  Inpil YOO ,  JooYang EOM

IPC: H01L25/00 ,  H01L25/18 ,  H01L23/367 ,  H01L23/467 ,  H01L23/473 ,  H01L25/07

Abstract: According to an aspect, a power module package includes a plurality of power modules including a first power module and a second power module, a plurality of heat sinks including a first heat sink coupled to the first power module and a second heat sink coupled to the second power module, and a module carrier coupled to the plurality of power modules, where the module carrier includes a first region defining a first heat-sink slot and a second region defining a second heat-sink slot. The first heat sink extends at least partially through the first heat-sink slot and the second heat sink extends at least partially through the second heat-sink slot. The power module package includes a housing coupled to the module carrier and a ring member located between the module carrier and the housing.

公开(公告)号：US20210111104A1

公开(公告)日：2021-04-15

申请号：US16677103

申请日：2019-11-07

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Inpil YOO ,  Seungwon IM ,  JooYang EOM ,  Jerome TEYSSEYRE

IPC: H01L23/495 ,  H01L23/00

Abstract: Implementations of a clip may include a first copper layer directly bonded to a first side of a ceramic layer, a second copper layer directly bonded to a second side of the ceramic layer, the second side of the ceramic layer opposite the first side of the ceramic layer, and a plurality of channels partially etched into a thickness of the second copper layer.