公开(公告)号：US20230069656A1

公开(公告)日：2023-03-02

申请号：US17702267

申请日：2022-03-23

Applicant: SK hynix Inc.

Inventor： Seon Ju LEE ,  Da Seul LEE

IPC: G11C11/406 ,  G11C11/4076 ,  G11C11/4096

Abstract: A data storage device may include a storage including a plurality of storage regions each composed of a plurality of pages; and a controller. The controller is configured to select a plurality of target open regions from open regions among the storage regions on the basis of health information of the open regions, in each of which a programmed page and an unprogrammed page coexist, and perform control so that refresh operations for the respective target open regions are performed in a time-distributed manner.

公开(公告)号：US20240232087A1

公开(公告)日：2024-07-11

申请号：US18328774

申请日：2023-06-05

Applicant: SK hynix Inc.

Inventor： Seon Ju LEE ,  Jeong Sun PARK

IPC: G06F12/0855

CPC classification number: G06F12/0855 ,  G06F2212/1016 ,  G06F2212/45

Abstract: Disclosed is an operation method of a storage device, which is for providing an optimal program/read efficiency in the storage device. The operation method includes: receiving program commands that request data write and data to be written from at least one first outside; storing sequentially the program commands in a command queue in the order in which they are received and storing in a temporary buffer, the data to be written; selecting one program command from among the program commands stored in the command queue; determining whether the selected program command is a continuous data program command or a discontinuous data program command; and allocating, if the selected program command is the continuous data program command, data to be written of the continuous data program command to an entire area of a stripe that is a memory area formed over a plurality of dies included in a second outside.

公开(公告)号：US20240232082A1

公开(公告)日：2024-07-11

申请号：US18337052

申请日：2023-06-19

Applicant: SK hynix Inc.

Inventor： Seon Ju LEE ,  Geon Woo KIM

IPC: G06F12/0811 ,  G06F12/0875

CPC classification number: G06F12/0811 ,  G06F12/0875 ,  G06F2212/1016

Abstract: The present disclosure relates to a storage device that optimally maintains a size of debugging data. Disclosed is a memory controller, including a first interface may communicate with a first external device; a second interface may generate a signal for controlling an operation of a second external device; a first volatile memory buffer; and a processor may generate and store the telemetry log data in the first volatile memory buffer; move and store the telemetry log data stored in the first volatile memory buffer to a first non-volatile memory buffer, when a size of the telemetry log data stored in the first volatile memory buffer is greater than or equal to a threshold size; and set the threshold size based on at least one among a number of telemetry logs stored in the first volatile memory buffer and a rising momentum of the number of the telemetry logs.

公开(公告)号：US20240012578A1

公开(公告)日：2024-01-11

申请号：US18077864

申请日：2022-12-08

Applicant: SK hynix Inc.

Inventor： Seon Ju LEE ,  Seung Geol BAEK ,  Jae Hyun YOO ,  Dong Kyu LEE

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0656 ,  G06F3/0658 ,  G06F3/0679 ,  G06F3/0604

Abstract: A data storage device may include a plurality of system resources, a buffer memory device and a memory controller. The buffer memory device may include a buffer memory allotted to the system resources. The memory controller may allocate the buffer memory based on performance requirements that are set in each of the system resources.

公开(公告)号：US20210065815A1

公开(公告)日：2021-03-04

申请号：US16696508

申请日：2019-11-26

Applicant: SK hynix Inc.

Inventor： Seon Ju LEE ,  Min Hwan MOON

IPC: G11C16/26 ,  G06F11/10 ,  G11C29/52

Abstract: A memory controller having improved read performance controls a memory device including a plurality of memory cells. The memory controller includes a read operation controller, a history bias storage, and a read voltage setting circuit. The read operation controller read data stored selected memory cells among the plurality of memory cells. The history bias storage stores a plurality of history mean biases, which are mean biases of a plurality of threshold voltage distributions that the plurality of memory cells have, and a plurality of reference cell count values respectively corresponding to the plurality of threshold voltage distributions.

公开(公告)号：US20200341842A1

公开(公告)日：2020-10-29

申请号：US16927106

申请日：2020-07-13

Applicant: SK Hynix Inc.

Inventor： Seon Ju LEE ,  Min Hwan MOON

IPC: G06F11/10 ,  G11C16/26 ,  G11C16/04 ,  G11C29/52 ,  G11C29/02

Abstract: A method for operating a memory system includes: performing a read operation in response to a first tag; performing a read operation in response to a second tag; performing a defense code operation corresponding to the first tag; performing an error correction code (KC) operation on data output through the defense code operation corresponding to the first tag; and performing a defense code operation corresponding to the second tag, wherein the read operation in response to the second tag is started before the ECC operation corresponding to the first tag is completed, and wherein the defense code operation corresponding to the second tag is performed using a result of the defense code operation corresponding to the first tag.

公开(公告)号：US20200043556A1

公开(公告)日：2020-02-06

申请号：US16384282

申请日：2019-04-15

Applicant: SK hynix Inc.

Inventor： Min Hwan MOON ,  Seon Ju LEE ,  Jung Chul HAN

IPC: G11C16/16 ,  G11C16/04 ,  G11C16/26 ,  G06F3/06

Abstract: In a memory controller configured to control a memory device including a plurality of memory blocks, the memory controller comprising: a memory interface configured to exchange data with the memory device; and a pre-program controller configured to perform a read operation on a last page of a program sequence for a plurality of pages in an erase target memory block when the memory device is in an idle state, and perform a pre-program operation on the erase target memory block according to the result obtained by performing the read operation, wherein the erase target memory block is a memory block on which an erase operation is to be performed among the plurality of memory blocks, and wherein the erase operation on the erase target memory block is performed after the pre-program operation is performed.

公开(公告)号：US20240419342A1

公开(公告)日：2024-12-19

申请号：US18815839

申请日：2024-08-27

Applicant: SK hynix Inc.

Inventor： Dong Kyu LEE ,  Seung Geol BAEK ,  Jae Hyun YOO ,  Seon Ju LEE

IPC: G06F3/06

Abstract: A memory system may include a memory device including a plurality of memory areas each configured by a plurality of memory blocks; and a memory controller configured to generate zones each including at least one memory block selected from at least one of the memory areas included in the memory device, manage configuration information for each generated zone, sequentially store data from a first storage location of an open zone among the generated zones during a write operation on the open zone according to an external request, and determine a number of active target memory areas associated with the open zone on a basis of configuration information of the open zone.

公开(公告)号：US20240036731A1

公开(公告)日：2024-02-01

申请号：US18082586

申请日：2022-12-16

Applicant: SK hynix Inc.

Inventor： Seon Ju LEE ,  Ki Tae KIM ,  In Ho JUNG

IPC: G06F3/06

CPC classification number: G06F3/061 ,  G06F3/0653 ,  G06F3/0679

Abstract: Provided herein may be a memory system and a method of operating the same. A memory controller may include a latency monitoring component configured to generate information about a number of occurrences of over-latency exceeding a preset reference latency among latencies each indicating a time amount required from a time point at which first command is received from an external device to a time point at which a completion response to the first command is transmitted to the external device during a first period, and a completion response controller configured to determine a first target latency based on the information about the number of occurrences of over-latency, and provide, during a second period following the first period, the external device with a completion response to a second commands provided from the external device after the first target latency has elapsed.

公开(公告)号：US20240028210A1

公开(公告)日：2024-01-25

申请号：US18058183

申请日：2022-11-22

Applicant: SK hynix Inc.

Inventor： Seon Ju LEE ,  Jeong Sun PARK

IPC: G06F3/06

CPC classification number: G06F3/0613 ,  G06F3/0659 ,  G06F3/0679

Abstract: A memory system may wait to receive one or more read commands from a reference time point, and read data, requested by the one or more read commands, from the memory device in response to a determination that it is possible to simultaneously read data divided and stored, as an M number of data units, in an M number of planes among a plurality of planes in response to the one or more read commands or that a maximum read wait time has elapsed from the reference time point, M being a natural number.