公开(公告)号：US20250077454A1

公开(公告)日：2025-03-06

申请号：US18951662

申请日：2024-11-19

Applicant: SK hynix Inc.

Inventor： Ki Sung KIM ,  Wun Mo YANG ,  Gun Woo YEON ,  Dong Kyu LEE

IPC: G06F13/28 ,  G06F13/42

Abstract: A Peripheral Component Interconnect express (PCIe) device includes a Direct Memory Access (DMA) device including a plurality of functions; and a PCIe interface device for performing communication between a host and the DMA device. The PCIe interface device includes a reset operation controller for, when a plurality of reset signals are received from the host, grouping operations, which are the same as one another among reset operations respectively corresponding to the plurality of reset signals, determining a processing order of the reset operations, and performing the reset operations according to the processing order.

公开(公告)号：US20230168827A1

公开(公告)日：2023-06-01

申请号：US17688689

申请日：2022-03-07

Applicant: SK hynix Inc.

Inventor： Dong Kyu LEE ,  Seung Geol BAEK ,  Jae Hyun YOO ,  Seon Ju LEE

IPC: G06F3/06

CPC classification number: G06F3/064 ,  G06F3/0659 ,  G06F3/0631 ,  G06F3/0604 ,  G06F3/0673

Abstract: A memory controller that controls a memory device including a plurality of memory blocks allocated to a plurality of zones for storing data is provided. The memory controller comprises a plurality of processing cores controlling data operations in the plurality of zones in the memory device; and an external interface unit in communication with an external device and configured to receive, from the external device, a write request requesting to perform a write operation on a first zone in the memory device, the external interface unit configured to identify a first processing core for controlling the first zone and determine a second core to perform the write operation based on a number of open zones controlled by the first core and having an open state indicating a capability to execute a program operation.

公开(公告)号：US20240012578A1

公开(公告)日：2024-01-11

申请号：US18077864

申请日：2022-12-08

Applicant: SK hynix Inc.

Inventor： Seon Ju LEE ,  Seung Geol BAEK ,  Jae Hyun YOO ,  Dong Kyu LEE

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0656 ,  G06F3/0658 ,  G06F3/0679 ,  G06F3/0604

Abstract: A data storage device may include a plurality of system resources, a buffer memory device and a memory controller. The buffer memory device may include a buffer memory allotted to the system resources. The memory controller may allocate the buffer memory based on performance requirements that are set in each of the system resources.

公开(公告)号：US20240419342A1

公开(公告)日：2024-12-19

申请号：US18815839

申请日：2024-08-27

Applicant: SK hynix Inc.

Inventor： Dong Kyu LEE ,  Seung Geol BAEK ,  Jae Hyun YOO ,  Seon Ju LEE

IPC: G06F3/06

Abstract: A memory system may include a memory device including a plurality of memory areas each configured by a plurality of memory blocks; and a memory controller configured to generate zones each including at least one memory block selected from at least one of the memory areas included in the memory device, manage configuration information for each generated zone, sequentially store data from a first storage location of an open zone among the generated zones during a write operation on the open zone according to an external request, and determine a number of active target memory areas associated with the open zone on a basis of configuration information of the open zone.

公开(公告)号：US20230297253A1

公开(公告)日：2023-09-21

申请号：US17882112

申请日：2022-08-05

Applicant: SK hynix Inc.

Inventor： Dong Kyu LEE ,  Seung Geol BAEK ,  Jae Hyun YOO ,  Seon Ju LEE

IPC: G06F3/06

CPC classification number: G06F3/0625 ,  G06F3/064 ,  G06F3/0679

Abstract: A memory system may include a memory device including a plurality of memory areas each configured by a plurality of memory blocks; and a memory controller configured to generate zones each including at least one memory block selected from at least one of the memory areas included in the memory device, manage configuration information for each generated zone, sequentially store data from a first storage location of an open zone among the generated zones during a write operation on the open zone according to an external request, and determine a number of active target memory areas associated with the open zone on a basis of configuration information of the open zone.

公开(公告)号：US20220187996A1

公开(公告)日：2022-06-16

申请号：US17355559

申请日：2021-06-23

Applicant: SK hynix Inc.

Inventor： Ki Sung KIM ,  Jae Hun KIM ,  Seung Geol BAEK ,  Dong Kyu LEE

IPC: G06F3/06

Abstract: The present disclosure relates to an electronic device, and more particularly, to a memory controller and a storage device including the same. According to an embodiment, a memory controller includes a storage configured to store first defect information corresponding to a non-repairable defect and second defect information corresponding to a repairable defect, an output circuit configured to detect a defect in the memory controller and to output the first or second defect information as defect information corresponding to a detected defect, and logic configured to check a type of the detected defect based on the second defect information when the defect information corresponds to the second defect information and to perform a recovery operation according to the type of the detected defect.