公开(公告)号：US20240078042A1

公开(公告)日：2024-03-07

申请号：US18160040

申请日：2023-01-26

Applicant: SK hynix Inc.

Inventor： Kang Rak KWON ,  Seon Ju LEE

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0673

Abstract: A storage device may fetch commands from a plurality of command queues. The storage device may determine a policy for fetching commands from the plurality of command queues as a first policy or a second policy on the basis of the state of a target command queue among the plurality of command queues. The policy may control an order in which commands are fetched from the plurality of command queues.

公开(公告)号：US20230418521A1

公开(公告)日：2023-12-28

申请号：US18070610

申请日：2022-11-29

Applicant: SK hynix Inc.

Inventor： In Ho JUNG ,  Ki Tae KIM ,  Seon Ju LEE

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0629 ,  G06F3/0611 ,  G06F3/0679

Abstract: A memory system comprising: a memory device having a nonvolatile specific storage space configured to store workload information including groups of parameter values, grouped respectively corresponding to a plurality of workload classes in a table form, and a controller configured to detect a ratio of a set command inputted from an outside in a set operation mode, select one of the workload classes as a detected class, load, from the specific storage space, one of the groups corresponding to the detected class, process the set command under an execution condition determined by applying the loaded group, and update the group corresponding to the detected class with parameter values inputted from the outside.

公开(公告)号：US20230075808A1

公开(公告)日：2023-03-09

申请号：US17686104

申请日：2022-03-03

Applicant: SK hynix Inc.

Inventor： Da Seul LEE ,  Seon Ju LEE ,  You Min JI

IPC: G11C7/10 ,  G11C7/04 ,  G11C11/4074

Abstract: A memory system and a method of operating the memory system are provided. The memory system may determine, on a determination that the memory system enters thermal throttling mode, a target status read check period based on threshold voltage distribution offset for the target memory die, and set a timer to transmit a status read command for the target memory die to the memory device based on the target status read check period.

公开(公告)号：US20240385753A1

公开(公告)日：2024-11-21

申请号：US18789141

申请日：2024-07-30

Applicant: SK Hynix Inc.

Inventor： Seon Ju LEE ,  Jeong Sun PARK

IPC: G06F3/06

Abstract: A memory system may wait to receive one or more read commands from a reference time point, and read data, requested by the one or more read commands, from the memory device in response to a determination that it is possible to simultaneously read data divided and stored, as an M number of data units, in an M number of planes among a plurality of planes in response to the one or more read commands or that a maximum read wait time has elapsed from the reference time point, M being a natural number.

公开(公告)号：US20240028219A1

公开(公告)日：2024-01-25

申请号：US18096563

申请日：2023-01-13

Applicant: SK hynix Inc.

Inventor： Dong Min BHAN ,  Seon Ju LEE

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0673 ,  G06F3/0656 ,  G06F3/064 ,  G06F3/0659

Abstract: Provided herein may be a memory controller and a memory system including the same. The memory controller may include a plurality of control cores configured to control a plurality of zone blocks respectively corresponding to logical address groups provided by a host, a buffer memory configured to store information about a zone group including zone blocks which are controlled by different control cores among the plurality of zone blocks, the information about zone group being generated based on information about an available space in each of the plurality of zone blocks, and a wear-leveling controller configured to control the plurality of control cores to perform a global wear-leveling operation of swapping pieces of data between the zone blocks included in the zone group based on a wear-level of the plurality of zone blocks.

公开(公告)号：US20230168827A1

公开(公告)日：2023-06-01

申请号：US17688689

申请日：2022-03-07

Applicant: SK hynix Inc.

Inventor： Dong Kyu LEE ,  Seung Geol BAEK ,  Jae Hyun YOO ,  Seon Ju LEE

IPC: G06F3/06

CPC classification number: G06F3/064 ,  G06F3/0659 ,  G06F3/0631 ,  G06F3/0604 ,  G06F3/0673

Abstract: A memory controller that controls a memory device including a plurality of memory blocks allocated to a plurality of zones for storing data is provided. The memory controller comprises a plurality of processing cores controlling data operations in the plurality of zones in the memory device; and an external interface unit in communication with an external device and configured to receive, from the external device, a write request requesting to perform a write operation on a first zone in the memory device, the external interface unit configured to identify a first processing core for controlling the first zone and determine a second core to perform the write operation based on a number of open zones controlled by the first core and having an open state indicating a capability to execute a program operation.

公开(公告)号：US20250123764A1

公开(公告)日：2025-04-17

申请号：US18611737

申请日：2024-03-21

Applicant: SK hynix Inc.

Inventor： Seon Ju LEE ,  Jeong Sun PARK

IPC: G06F3/06

Abstract: Provided herein is a semiconductor memory device having improved lifespan. The storage device may include a memory device including a plurality of super blocks, and a controller configured to control the memory device in response to each request among a plurality of requests from a host, wherein the controller is further configured to allocate a first super block to a first write request of a first type, and allocate a second super block different from the first super block to respond to a second write request of a second type, control the memory device to store in the first super block write data corresponding to the first write request, and when the second write request is received from the host before reallocation of the second super block after deallocation, control the memory device to store in the first super block write data corresponding to the second write request.

公开(公告)号：US20240127897A1

公开(公告)日：2024-04-18

申请号：US18188475

申请日：2023-03-23

Applicant: SK hynix Inc.

Inventor： Seon Ju LEE

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/10 ,  G11C16/20

CPC classification number: G11C16/3459 ,  G11C16/0433 ,  G11C16/102 ,  G11C16/20

Abstract: A memory device comprises: a plurality of memory blocks each including a plurality of word lines, a control operation circuit suitable for performing a read operation on each of the plurality of word lines, and a control logic suitable for: storing a plurality of default levels, which respectively correspond to the memory blocks, in an information storage region therein, controlling the control operation circuit to perform one of a first read operation using a selected default level corresponding to a selected block and a second read operation using an adjusted level smaller than the selected default level, resetting the adjusted level to the selected default level when a number of times that the second read operation is passed is greater than a number of times that the first read operation is passed, by a reference number of times or more, and storing the reset level in the information storage region.

公开(公告)号：US20240126682A1

公开(公告)日：2024-04-18

申请号：US18190979

申请日：2023-03-28

Applicant: SK hynix Inc.

Inventor： Seon Ju LEE ,  Min Hwan MOON

IPC: G06F12/02 ,  G06F11/14

CPC classification number: G06F12/023 ,  G06F11/1415 ,  G06F2201/805 ,  G06F2212/251

Abstract: A storage device may include: a plurality of memory dies; and a memory controller for receiving a first read request from a first function, controlling at least one memory die to perform a read operation according to the first read request, and controlling, when receiving a second read request from a second function in the course of the read operation according to the first read request, the at least one memory die to suspend the read operation according to the first read request and to perform a read operation according to the second read request based on a result obtained by comparing performance requirement information of the second function with residual time information of the second read request, which is determined according to a performance degree of the read operation being performed according to the first read request.

公开(公告)号：US20230384937A1

公开(公告)日：2023-11-30

申请号：US18081605

申请日：2022-12-14

Applicant: SK hynix Inc.

Inventor： Seon Ju LEE ,  Seung Geol Baek ,  Jae Hyun Yoo ,  Dong Kyu Lee

IPC: G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/0679 ,  G06F3/0653

Abstract: The present technology relates to an electronic device. According to the present technology, a memory controller may include a latency monitor and an operation controller. The latency monitor may count an over-latency count value representing a number of over-latencies exceeding a reference value among latencies for requests from a host during each of a plurality of periods, calculate gaps which are difference values between the over-latency count values of the plurality of periods, and generate latency information including the over-latency count values and the gaps. The operation controller may determine, based on the latency info oration, whether each gap between at least two target periods among the plurality of periods exceeds a threshold value, and delay a response to the requests according to a determination result.