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    SEMICONDUCTOR MEMORY DEVICE
    11.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20190287977A1

    公开(公告)日：2019-09-19

    申请号：US16419947

    申请日：2019-05-22

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kiseok LEE ,  Chan-Sic YOON ,  Augustin HONG ,  Keunnam KIM ,  Dongoh KIM ,  Bong-Soo KIM ,  Jemin PARK ,  Hoin LEE ,  Sungho JANG ,  Kiwook JUNG ,  Yoosang HWANG

    IPC: H01L27/108

    Abstract: A method of manufacturing a semiconductor memory device and a semiconductor memory device, the method including providing a substrate that includes a cell array region and a peripheral circuit region; forming a mask pattern that covers the cell array region and exposes the peripheral circuit region; growing a semiconductor layer on the peripheral circuit region exposed by the mask pattern such that the semiconductor layer has a different lattice constant from the substrate; forming a buffer layer that covers the cell array region and exposes the semiconductor layer; forming a conductive layer that covers the buffer layer and the semiconductor layer; and patterning the conductive layer to form conductive lines on the cell array region and to form a gate electrode on the peripheral circuit region.

    METHODS OF FABRICATING SEMICONDUCTOR MEMORY DEVICES
    12.
    发明申请
    METHODS OF FABRICATING SEMICONDUCTOR MEMORY DEVICES 审中-公开

    公开(公告)号：US20180301459A1

    公开(公告)日：2018-10-18

    申请号：US15952350

    申请日：2018-04-13

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Eunjung KIM ,  Daeik KIM ,  Bong-Soo KIM ,  Jemin PARK ,  Semyeong JANG ,  Yoosang HWANG

    IPC: H01L27/108 ,  H01L21/768 ,  H01L21/02 ,  B08B7/00

    Abstract: A method of fabricating a semiconductor memory device includes forming a bit line and a bit line capping pattern on the semiconductor substrate, forming a first spacer covering a sidewall of the bit line capping pattern and a sidewall of the bit line, forming a contact plug in contact with a sidewall of the first spacer and having a top surface that is lower than an upper end of the first spacer, removing an upper portion of the first spacer, forming a first sacrificial layer closing at least an entrance of the void, forming a second spacer covering the sidewall of the bit line capping pattern and having a bottom surface in contact with a top surface of the first spacer, and removing the first sacrificial layer. The bit line capping pattern is on the bit line. The contact plug includes a void exposed on the top surface.

    FINFET SEMICONDUCTOR DEVICES AND METHOD OF FORMING THE SAME
    13.
    发明申请
    FINFET SEMICONDUCTOR DEVICES AND METHOD OF FORMING THE SAME 有权
    FINFET半导体器件及其形成方法

    公开(公告)号：US20170069737A1

    公开(公告)日：2017-03-09

    申请号：US15236726

    申请日：2016-08-15

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kyung-In CHOI ,  Bong-Soo KIM ,  Hyun-Seung KIM ,  Hyun-Gi HONG

    IPC: H01L29/66 ,  H01L29/08 ,  H01L21/02 ,  H01L21/225

    CPC classification number: H01L29/66803 ,  H01L21/02175 ,  H01L21/02244 ,  H01L21/02252 ,  H01L21/2255 ,  H01L21/2256 ,  H01L29/0847 ,  H01L29/66492 ,  H01L29/66545 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

    Abstract: Provided are a semiconductor device and a method of fabricating the same. The method comprises forming an active fin extending along a first direction; forming a field insulating layer exposing an upper part of the active fin, along long sides of the active fin; forming a dummy gate pattern extending along a second direction intersecting the first direction, on the active fin; forming a spacer on at least one side of the dummy gate pattern; forming a liner layer covering the active fin exposed by the spacer and the dummy gate pattern; forming a dopant supply layer containing a dopant element, on the liner layer; and forming a doped region in the active fin along an upper surface of the active fin by heat-treating the dopant supply layer.

    Abstract translation: 提供半导体器件及其制造方法。 该方法包括形成沿着第一方向延伸的活性翅片; 形成沿有源鳍片的长边暴露活性鳍片的上部的场绝缘层; 在所述活动翅片上形成沿着与所述第一方向相交的第二方向延伸的虚拟栅极图案; 在所述伪栅极图案的至少一侧上形成间隔物; 形成覆盖由所述间隔物和所述伪栅极图案露出的所述有源鳍的衬垫层; 在所述衬垫层上形成含有掺杂剂元素的掺杂剂供给层; 以及通过热处理所述掺杂剂供应层，沿着所述活性鳍片的上表面在所述活性鳍片中形成掺杂区域。

    SEMICONDUCTOR MEMORY DEVICES
    15.
    发明申请
    SEMICONDUCTOR MEMORY DEVICES 审中-公开

    公开(公告)号：US20190164985A1

    公开(公告)日：2019-05-30

    申请号：US16027887

    申请日：2018-07-05

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kiseok LEE ,  Junsoo KIM ,  Hui-Jung KIM ,  Bong-Soo KIM ,  Satoru YAMADA ,  Kyupil LEE ,  Sunghee HAN ,  HyeongSun HONG ,  Yoosang HWANG

    IPC: H01L27/11556 ,  H01L23/532 ,  H01L27/11524 ,  H01L49/02 ,  G11C8/14 ,  G11C7/18

    Abstract: A semiconductor memory device comprises a stack structure including a plurality of layers vertically stacked on a substrate. Each of the plurality of layers includes a first dielectric layer, a semiconductor layer, and a second dielectric layer that are sequentially stacked, and a first conductive line in the second dielectric layer and extending in a first direction. The device also comprises a second conductive line extending vertically through the stack structure, and a capacitor in the stack structure and spaced apart from the second conductive line. The semiconductor layer comprises semiconductor patterns extending in a second direction intersecting the first direction between the first conductive line and the substrate. The second conductive line is between a pair of the semiconductor patterns adjacent to each other in the first direction. An end of each of the semiconductor patterns is electrically connected to a first electrode of the capacitor.

    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
    17.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 审中-公开
    半导体器件及其制造方法

    公开(公告)号：US20170005097A1

    公开(公告)日：2017-01-05

    申请号：US15196273

    申请日：2016-06-29

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Eun-Jung KIM ,  Bong-Soo KIM ,  Yong-Kwan KIM ,  Sung-Hee HAN ,  Yoo-Sang HWANG

    IPC: H01L27/108 ,  H01L21/768 ,  H01L23/532 ,  H01L23/528 ,  H01L23/522

    Abstract: A semiconductor device, including an active region defined in a semiconductor substrate; a first contact plug on the semiconductor substrate, the first contact plug being connected to the active region; a bit line on the semiconductor substrate, the bit line being adjacent to the first contact plug; a first air gap spacer between the first contact plug and the bit line; a landing pad on the first contact plug; a blocking insulating layer on the bit line; and an air gap capping layer on the first air gap spacer, the air gap capping layer vertically overlapping the first air gap spacer, the air gap capping layer being between the blocking insulating layer and the landing pad, an upper surface of the blocking insulating layer being at a height equal to or higher than an upper surface of the landing pad.

    Abstract translation: 一种半导体器件，包括限定在半导体衬底中的有源区; 在所述半导体衬底上的第一接触插塞，所述第一接触插塞连接到所述有源区; 所述半导体衬底上的位线，所述位线与所述第一接触插塞相邻; 在所述第一接触插塞和所述位线之间的第一气隙间隔件; 第一接触塞上的着陆垫; 位线上的阻挡绝缘层; 以及在所述第一气隙间隔件上的气隙盖层，所述气隙盖层与所述第一气隙间隔件垂直重叠，所述气隙盖层位于所述阻挡绝缘层和所述着陆焊盘之间，所述阻挡绝缘层的上表面 处于与着陆垫的上表面相同或更高的高度。

    INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING THE SAME
    19.
    发明申请
    INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开

    公开(公告)号：US20200243532A1

    公开(公告)日：2020-07-30

    申请号：US16851957

    申请日：2020-04-17

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hui-Jung KIM ,  Sung-hee HAN ,  Ki-seok LEE ,  Bong-Soo KIM ,  Yoo-sang HWANG

    IPC: H01L27/108 ,  H01L49/02

    Abstract: An integrated circuit device may include a support pattern over a substrate, a lower electrode pattern and a dielectric structure over the substrate, and an upper electrode structure on the dielectric structure. The support pattern may include a first support structure extending in a vertical direction. The lower electrode pattern may be between the support pattern and the dielectric structure. The lower electrode pattern may include a first group of N (e.g., an integer of 4 or more) lower electrodes that are spaced apart from each other and may extend in the vertical direction to a first level above the substrate. The dielectric structure may include a first dielectric protrusion that extends in the vertical direction and surrounds the first support structure and the first group of N lower electrodes. The upper electrode structure may include a first upper electrode protrusion that surrounds the first dielectric protrusion.

    SEMICONDUCTOR MEMORY DEVICES
    20.
    发明申请
    SEMICONDUCTOR MEMORY DEVICES 审中-公开

    公开(公告)号：US20190103407A1

    公开(公告)日：2019-04-04

    申请号：US16038052

    申请日：2018-07-17

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jiyoung KIM ,  Kiseok LEE ,  Bong-Soo KIM ,  Junsoo KIM ,  Dongsoo WOO ,  Kyupil LEE ,  HyeongSun HONG ,  Yoosang HWANG

    IPC: H01L27/108

    CPC classification number: H01L27/10805 ,  H01L27/0688 ,  H01L27/1085 ,  H01L28/86

    Abstract: Semiconductor memory devices are provided. A semiconductor memory device includes a substrate. The semiconductor memory device includes a plurality of memory cell transistors vertically stacked on the substrate. The semiconductor memory device includes a first conductive line connected to a source region of at least one of the plurality of memory cell transistors. The semiconductor memory device includes a second conductive line connected to a plurality of gate electrodes of the plurality of memory cell transistors. Moreover, the semiconductor memory device includes a data storage element connected to a drain region of the at least one of the plurality of memory cell transistors.

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