公开(公告)号：US20210408037A1

公开(公告)日：2021-12-30

申请号：US17172458

申请日：2021-02-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wukang Kim ,  Sejun Park ,  Hyoje Bang ,  Jaeduk Lee ,  Junghoon Lee

IPC: H01L27/11582 ,  H01L23/522 ,  H01L23/535

Abstract: A semiconductor device including a stack structure including gate layers and interlayer insulating layers spaced apart in a vertical direction, a channel hole penetrating the stack structure in the vertical direction, a core region extending within the channel hole, a channel layer disposed on a side surface of the core region, a first dielectric layer, a data storage layer and a second dielectric layer, which are disposed between the channel layer and the gate layers, and a pad pattern disposed on the core region, in the channel hole, and in contact with the channel layer. A first horizontal distance between a side surface of a first portion of an uppermost gate layer and an outer side surface of the channel layer is greater than a second horizontal distance between a side surface of a second portion of the uppermost gate layer and an outer side surface of the pad pattern.

公开(公告)号：US20190363012A1

公开(公告)日：2019-11-28

申请号：US16534195

申请日：2019-08-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dohyun Lee ,  Youngwoo Park ,  Junghoon Park ,  Jaeduk Lee

IPC: H01L21/768 ,  H01L27/11582 ,  H01L27/11575 ,  H01L27/11573 ,  H01L27/1157 ,  H01L23/532 ,  H01L23/522

Abstract: A semiconductor device includes a semiconductor pattern on a semiconductor substrate, a three-dimensional memory array on the semiconductor pattern, and a peripheral interconnection structure between the semiconductor pattern and the semiconductor substrate. The peripheral interconnection structure includes an upper interconnection structure on a lower interconnection structure. The upper interconnection structure includes an upper interconnection and an upper barrier layer. The lower interconnection structure includes a lower interconnection and a lower barrier layer. The upper barrier layer is under a bottom surface of the upper interconnection and does not cover side surfaces of the upper interconnection. The lower barrier layer is under a bottom surface of the lower interconnection and covers side surfaces of the lower interconnection.

公开(公告)号：US09595346B2

公开(公告)日：2017-03-14

申请号：US15157720

申请日：2016-05-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changhyun Lee ,  Dohyun Lee ,  Youngwoo Park ,  Su Jin Ahn ,  Jaeduk Lee

IPC: G11C11/34 ,  G11C16/34 ,  G11C16/10 ,  G11C16/04 ,  H01L27/115 ,  H01L23/528 ,  H01L29/04 ,  H01L29/16

CPC classification number: H01L27/11524 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3459 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/04 ,  H01L29/16

Abstract: Disclosed is a three-dimensional semiconductor memory device, comprising a cell array formed on a first substrate and a peripheral circuit formed on a second substrate that is at least partially overlapped by the first substrate, wherein the peripheral circuit is configured to provide signals for controlling the cell array. The cell array comprises insulating patterns and gate patterns stacked alternately on the first substrate, and at least a first pillar formed in a direction perpendicular to the first substrate and being in contact with the first substrate through the insulating patterns and the gate patterns. The three-dimensional semiconductor memory device further comprising a first ground selection transistor that includes a first gate pattern, adjacent to the first substrate and the first pillar, and a second ground selection transistor that includes a second gate pattern positioned on the first gate pattern and the first pillar, and wherein the first ground selection transistor is not programmable, and the second ground selection transistor is programmable.

Abstract translation: 公开了一种三维半导体存储器件，包括形成在第一衬底上的单元阵列和形成在第二衬底上的外围电路，所述外围电路至少部分地与第一衬底重叠，其中外围电路被配置为提供控制信号 单元格阵列。 电池阵列包括在第一衬底上交替堆叠的绝缘图案和栅极图案，以及至少第一柱，其沿垂直于第一衬底的方向形成，并且通过绝缘图案和栅极图案与第一衬底接触。 所述三维半导体存储器件还包括第一接地选择晶体管，其包括与所述第一衬底和所述第一柱相邻的第一栅极图案，以及第二接地选择晶体管，所述第二接地选择晶体管包括位于所述第一栅极图案上的第二栅极图案， 第一支柱，并且其中第一接地选择晶体管不可编程，并且第二接地选择晶体管是可编程的。

公开(公告)号：US20250048639A1

公开(公告)日：2025-02-06

申请号：US18653301

申请日：2024-05-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hakseon Kim ,  Kangoh Yun ,  Dongjin Lee ,  Youngrok Kim ,  Ryoongbin Lee ,  Jaeduk Lee

IPC: H10B43/40 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27

Abstract: A non-volatile memory device includes a peripheral circuit and a memory cell array that are sequentially stacked. The peripheral circuit includes, a device isolation layer defining an active region within a substrate, a first gate electrode extending in a first horizontal direction on the active region, an insulating pattern in a first recess and a second recess spaced apart in a second horizontal direction within the active region on opposing sides of the first gate electrode, a first low concentration doped region along an outer wall of the first recess, a second low concentration doped region along an outer wall of the second recess, a first source/drain region buried in the first low concentration doped region, and a second source/drain region buried in the second low concentration doped region.

公开(公告)号：US11950417B2

公开(公告)日：2024-04-02

申请号：US17172458

申请日：2021-02-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wukang Kim ,  Sejun Park ,  Hyoje Bang ,  Jaeduk Lee ,  Junghoon Lee

IPC: H01L29/423 ,  H01L23/522 ,  H01L23/535 ,  H01L27/11524 ,  H10B43/27 ,  H10B43/35

CPC classification number: H10B43/27 ,  H01L23/5226 ,  H01L23/535 ,  H10B43/35

Abstract: A semiconductor device including a stack structure including gate layers and interlayer insulating layers spaced apart in a vertical direction, a channel hole penetrating the stack structure in the vertical direction, a core region extending within the channel hole, a channel layer disposed on a side surface of the core region, a first dielectric layer, a data storage layer and a second dielectric layer, which are disposed between the channel layer and the gate layers, and a pad pattern disposed on the core region, in the channel hole, and in contact with the channel layer. A first horizontal distance between a side surface of a first portion of an uppermost gate layer and an outer side surface of the channel layer is greater than a second horizontal distance between a side surface of a second portion of the uppermost gate layer and an outer side surface of the pad pattern.

公开(公告)号：US11348930B2

公开(公告)日：2022-05-31

申请号：US16668222

申请日：2019-10-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Janggn Yun ,  Jaeduk Lee

IPC: H01L27/11548 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11575 ,  H01L27/11519 ,  H01L27/11565 ,  H01L23/522

Abstract: A semiconductor device includes a substrate including a memory cell region and a connection region, a plurality of gate electrodes stacked on the substrate, a channel structure penetrating the plurality of gate electrodes and including a channel layer extending in a vertical direction perpendicular to an upper surface of the substrate in the memory cell region, a dummy channel structure penetrating the plurality of gate electrodes and including a dummy channel layer extending in the vertical direction in the connection region, a first semiconductor layer disposed between the substrate and a lowermost one of the plurality of gate electrodes and surrounding the channel structure in the memory cell region, and an insulating separation structure disposed between the substrate and the lowermost one of the plurality of gate electrodes and surrounding the dummy channel layer.

公开(公告)号：US10707126B2

公开(公告)日：2020-07-07

申请号：US16751744

申请日：2020-01-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dohyun Lee ,  Youngwoo Park ,  Junghoon Park ,  Jaeduk Lee

IPC: H01L21/00 ,  H01L21/768 ,  H01L23/532 ,  H01L23/522 ,  H01L27/11582 ,  H01L27/11575 ,  H01L27/11573 ,  H01L27/1157 ,  H01L23/528

Abstract: A semiconductor device includes a semiconductor pattern on a semiconductor substrate, a three-dimensional memory array on the semiconductor pattern, and a peripheral interconnection structure between the semiconductor pattern and the semiconductor substrate. The peripheral interconnection structure includes an upper interconnection structure on a lower interconnection structure. The upper interconnection structure includes an upper interconnection and an upper barrier layer. The lower interconnection structure includes a lower interconnection and a lower barrier layer. The upper barrier layer is under a bottom surface of the upper interconnection and does not cover side surfaces of the upper interconnection. The lower barrier layer is under a bottom surface of the lower interconnection and covers side surfaces of the lower interconnection.

公开(公告)号：US09837429B2

公开(公告)日：2017-12-05

申请号：US15348009

申请日：2016-11-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yunghwan Son ,  Jaesung Sim ,  Shinhwan Kang ,  Youngwoo Park ,  Jaeduk Lee

IPC: H01L27/11575 ,  H01L27/11582 ,  H01L27/11573 ,  G11C16/30 ,  H01L29/34 ,  H01L27/11526 ,  G11C5/02 ,  G11C16/04 ,  H01L27/11517 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11551

CPC classification number: H01L27/11575 ,  G11C5/025 ,  G11C16/0483 ,  G11C16/30 ,  H01L27/11517 ,  H01L27/11526 ,  H01L27/11548 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582 ,  H01L29/34

Abstract: A three-dimensional (3D) semiconductor memory device that includes a peripheral logic structure including peripheral logic circuits disposed on a semiconductor substrate and a first insulation layer overlapping the peripheral logic circuits, and a plurality of memory blocks spaced apart from each other on the peripheral logic structure. At least one of the memory blocks includes a well plate electrode, a semiconductor layer in contact with a first surface of the well plate electrode, a stack structure including a plurality of electrodes vertically stacked on the semiconductor layer, and a plurality of vertical structures penetrating the stack structure and connected to the semiconductor layer.

公开(公告)号：US09082750B2

公开(公告)日：2015-07-14

申请号：US14218293

申请日：2014-03-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Albert Fayrushin ,  Kwang Soo Seol ,  Jaeduk Lee

IPC: H01L29/788 ,  H01L29/76 ,  H01L29/423 ,  H01L27/115 ,  H01L29/66 ,  H01L29/792

CPC classification number: H01L29/4234 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42336 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/7883 ,  H01L29/792

Abstract: Provided is a semiconductor device. The semiconductor device includes a substrate, a tunnel insulating layer, a charge storage pattern, a blocking layer, a gate electrode. The tunnel insulating layer is disposed over the substrate. The charge storage pattern is disposed over the tunnel insulating layer. The charge storage pattern has an upper surface, a sidewall, and an edge portion between the upper surface and the sidewall. The blocking layer includes an insulating pattern covering the edge portion of the charge storage pattern, and a gate dielectric layer covering the upper surface, the sidewall, and the edge portion of the charge storage pattern. The gate electrode is disposed over the blocking layer, the gate electrode covering the upper surface, the sidewall, and the edge portion of the charge storage pattern.

Abstract translation: 提供一种半导体器件。 半导体器件包括衬底，隧道绝缘层，电荷存储图案，阻挡层，栅电极。 隧道绝缘层设置在衬底上。 电荷存储图案设置在隧道绝缘层上。 电荷存储图案具有在上表面和侧壁之间的上表面，侧壁和边缘部分。 阻挡层包括覆盖电荷存储图案的边缘部分的绝缘图案，以及覆盖电荷存储图案的上表面，侧壁和边缘部分的栅极电介质层。 栅电极设置在阻挡层上，栅电极覆盖电荷存储图案的上表面，侧壁和边缘部分。

公开(公告)号：US20140197471A1

公开(公告)日：2014-07-17

申请号：US14218293

申请日：2014-03-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Albert Fayrushin ,  Kwang Soo Seol ,  Jaeduk Lee

IPC: H01L29/423 ,  H01L29/792 ,  H01L29/788

CPC classification number: H01L29/4234 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42336 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/7883 ,  H01L29/792

Abstract: Provided is a semiconductor device. The semiconductor device includes a substrate, a tunnel insulating layer, a charge storage pattern, a blocking layer, a gate electrode. The tunnel insulating layer is disposed over the substrate. The charge storage pattern is disposed over the tunnel insulating layer. The charge storage pattern has an upper surface, a sidewall, and an edge portion between the upper surface and the sidewall. The blocking layer includes an insulating pattern covering the edge portion of the charge storage pattern, and a gate dielectric layer covering the upper surface, the sidewall, and the edge portion of the charge storage pattern. The gate electrode is disposed over the blocking layer, the gate electrode covering the upper surface, the sidewall, and the edge portion of the charge storage pattern.

Abstract translation: 提供一种半导体器件。 半导体器件包括衬底，隧道绝缘层，电荷存储图案，阻挡层，栅电极。 隧道绝缘层设置在衬底上。 电荷存储图案设置在隧道绝缘层上。 电荷存储图案具有在上表面和侧壁之间的上表面，侧壁和边缘部分。 阻挡层包括覆盖电荷存储图案的边缘部分的绝缘图案，以及覆盖电荷存储图案的上表面，侧壁和边缘部分的栅极电介质层。 栅电极设置在阻挡层上，栅电极覆盖电荷存储图案的上表面，侧壁和边缘部分。