公开(公告)号：US20250151426A1

公开(公告)日：2025-05-08

申请号：US18782845

申请日：2024-07-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changkyu Lee ,  Jinyoung Kim ,  Byoungho Kwon ,  Jihun Lim

IPC: H01L27/146

Abstract: An image sensor includes a substrate, a unit pixel region in the substrate, the unit pixel region including a photoelectric conversion region, a pixel isolation structure defining the unit pixel region, a first insulation layer on a front-side surface of the substrate, and a dual transfer gate electrode including a first sub transfer gate electrode and a second sub transfer gate electrode adjacent to each other in a horizontal direction each passing through the first insulation layer and buried in the substrate, in the unit pixel region, wherein a lower surface of each of the first and the second sub transfer gate electrode is disposed at a lower vertical level than an upper surface of the first insulation layer, and at a higher or equal vertical level than a lower surface of the first insulation layer.

公开(公告)号：US20250054563A1

公开(公告)日：2025-02-13

申请号：US18655941

申请日：2024-05-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sehwan Park ,  Jinyoung Kim ,  Jisang Lee ,  Hyojung Jang

IPC: G11C29/52 ,  G11C7/10 ,  G11C7/22

Abstract: A memory device includes a memory cell array, a control logic which controls a read operation to read hard decision data and soft decision data from each page, and a page buffer which includes a first latch related to sensing of the hard decision data and a second latch related to sensing of the soft decision data. The control logic controls performing a first sensing operation of storing a value determined based on a first offset level, in the second latch, at a first sensing timing, and a second sensing operation of storing a value determined based on a second offset level, in the second latch, at a second sensing timing, and performs a control operation to provide a set signal SET to the second latch in the first sensing operation, and provide a reset signal RST to the second latch in the second sensing operation.

公开(公告)号：US20230411267A1

公开(公告)日：2023-12-21

申请号：US18128069

申请日：2023-03-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jiyeong Kim ,  Jinyoung Kim ,  Jihye Shim ,  Okseon Yoon

IPC: H01L23/498 ,  H01L25/10 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L23/49894 ,  H01L25/105 ,  H01L23/49816 ,  H01L24/08 ,  H01L24/16 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2224/08235 ,  H01L2224/16235 ,  H01L2924/182

Abstract: A semiconductor package includes a redistribution structure including a wiring structure and an insulating structure covering the wiring structure, the redistribution structure having a first surface and a second surface, which are opposite to each other, the insulating structure including a polymer, a semiconductor chip on the first surface, the semiconductor chip being connected to at least one first wiring pattern in the wiring structure, a passivation insulating film covering the second surface, the passivation insulating film including an inner surface contacting the insulating structure and a hole sidewall defining a hole, the passivation insulating film including an inorganic insulating material, a conductive pad passing through the passivation insulating film via the hole and contacting the second wiring pattern, the conductive pad having a pad sidewall contacting the hole sidewall, and an external connection terminal on the conductive pad.

公开(公告)号：US11815982B2

公开(公告)日：2023-11-14

申请号：US17968912

申请日：2022-10-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wandong Kim ,  Jinyoung Kim ,  Sehwan Park ,  Hyun Seo ,  Sangwan Nam

IPC: G11C7/00 ,  G06F11/07 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  G11C11/56 ,  G11C16/34

CPC classification number: G06F11/0727 ,  G06F11/076 ,  G06F11/0757 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  G11C11/56 ,  G11C16/34

Abstract: An operating method of a nonvolatile memory device for programming multi-page data, the operating method including: receiving the multi-page data from a memory controller; programming first page data among the multi-page data to first memory cells connected to a word line adjacent to a selected word line; reading previous page data previously stored in second memory cells connected to the selected word line based on a first sensing value and a second sensing value after programming the first page data; calculating a first fail bit number by comparing first bits of the previous page data read based on the first sensing value to second bits of the previous page data read based on the second sensing value; and programming the previous page data read from the second memory cells and second page data among the multi-page data to the second memory cells based on the first fail bit number.

公开(公告)号：US11682467B2

公开(公告)日：2023-06-20

申请号：US17353583

申请日：2021-06-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinyoung Kim ,  Sehwan Park ,  Youngdeok Seo ,  Ilhan Park

IPC: G11C16/26 ,  G11C29/42 ,  G11C16/04 ,  G11C16/08 ,  G11C16/24 ,  G11C16/34 ,  G11C29/44

CPC classification number: G11C29/42 ,  G11C16/0433 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26 ,  G11C16/3495 ,  G11C29/4401

Abstract: A nonvolatile memory device includes a plurality of memory blocks and a control logic circuit configured to perform a first page on-chip valley search (OVS) operation on memory cells connected to one wordline of a memory block selected in response to an address, among the plurality of memory blocks, in response to a first read command. The control logic circuit is further configured to change a read level of at least one state using detection information of the first page OVS operation, and to perform a second page read operation on the memory cells using the changed read level in response to a second read command.

公开(公告)号：US20230154841A1

公开(公告)日：2023-05-18

申请号：US17823634

申请日：2022-08-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Okseon Yoon ,  Jiyeong Kim ,  Jinyoung Kim

IPC: H01L23/498 ,  H01L25/18

CPC classification number: H01L23/49838 ,  H01L23/49822 ,  H01L25/18 ,  H01L24/16 ,  H01L2224/16145 ,  H01L2224/16227

Abstract: A semiconductor package includes: a redistribution structure including a plurality of redistribution insulation layers, which are stacked, a plurality of redistribution line patterns on an upper surface and a lower surface of the plurality of redistribution insulation layers, and constituting a plurality of distribution layers at different vertical levels from each other, and a plurality of redistribution vias that penetrate at least one redistribution insulation layer of the plurality of redistribution insulation layers and are connected to some of the plurality of redistribution line patterns; and at least one semiconductor chip on the redistribution structure and electrically connected to the plurality of redistribution line patterns and the plurality of redistribution vias.

公开(公告)号：US20230153205A1

公开(公告)日：2023-05-18

申请号：US18156893

申请日：2023-01-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dongmin SHIN ,  Jinyoung Kim ,  Sehwan Park

IPC: G06F11/10 ,  H03M13/45

CPC classification number: G06F11/1068 ,  H03M13/45

Abstract: A controller including a non-volatile memory interface circuit connected to at least one non-volatile memory device and configured to control the at least one non-volatile memory device; an error correction circuit configured to perform an error correction operation on a codeword received from the non-volatile memory interface circuit according to an error correction decoding level from among a plurality of error correction decoding levels, wherein the non-volatile memory interface circuit is further configured to: receive side information from the at least one non-volatile memory device; predict a distribution of memory cells based on the side information; and select the error correction decoding level from among the plurality of error correction decoding levels according to the predicted distribution.

公开(公告)号：US11562804B2

公开(公告)日：2023-01-24

申请号：US17469422

申请日：2021-09-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sehwan Park ,  Jinyoung Kim ,  Youngdeok Seo ,  Dongmin Shin ,  Joonsuc Jang ,  Sungmin Joe

IPC: G11C29/42 ,  G11C29/44 ,  G11C29/18 ,  G11C16/10 ,  G11C29/12 ,  G11C16/26

Abstract: A storage device includes a nonvolatile memory device and a memory controller to control the nonvolatile memory device. The nonvolatile memory device includes a memory cell array. The memory cell array includes a normal cell region, a parity cell region and a redundancy cell region. First bit-lines are connected to the normal cell region and the parity cell region and second bit-lines are connected to the redundancy cell region. The memory controller includes an error correction code (ECC) engine to generate parity data. The memory controller stores user data in the normal cell region, controls the nonvolatile memory device to perform a column repair on first defective bit-lines among the first bit-lines, assigns additional column addresses to the first defective bit-lines and the second bit-lines and stores at least a portion of the parity data in a region corresponding to the additionally assigned column addresses.

公开(公告)号：US20220222138A1

公开(公告)日：2022-07-14

申请号：US17397321

申请日：2021-08-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sehwan PARK ,  Jinyoung Kim ,  Ilhan Park ,  Youngdeok Seo

IPC: G06F11/10 ,  G06F3/06 ,  G11C16/04 ,  G11C16/26

Abstract: A memory device may determine cell count information from a threshold voltage distribution of memory cells and may determine a detection case based on the cell count information when an error in read data, received from the memory device performing a read operation is not corrected. A memory controller may control the memory device to execute a read operation using a development time determined in consideration of an offset voltage of a read voltage corresponding to the detection case. When an error in the read data is successfully corrected, the memory controller may update a table, stored in the memory controller, using a dynamic offset voltage obtained by inputting the cell count information to a machine learning model.

公开(公告)号：US12260790B2

公开(公告)日：2025-03-25

申请号：US17942775

申请日：2022-09-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Changjoon Lee ,  Seongho Son ,  Jongsung Lee ,  Jinyoung Kim ,  Youngki Jung

IPC: G09G3/00 ,  G06F3/14 ,  G09G3/32

Abstract: A display panel in which a resistance structure is provided on a test pattern to prevent a circuit of the display panel from being damaged by static electricity introduced into the test pattern, and a display apparatus having the same are provided. The display panel includes: a substrate; a plurality of pixel circuits provided on the substrate and configured to drive a plurality of inorganic light emitting devices; a test line provided on the substrate and extending from an edge of the substrate; an insulating layer provided on the test line; and a resistance structure provided on the test line, the resistance structure including: at least two vertical interconnect accesses (vias) passing through the insulating layer, and a resistance layer provided on the insulating layer and extending between the at least two vias, wherein the at least two vias connect the test line and the resistance layer to each other, and the test line is discontinuous at an area between the at least two vias, and wherein the resistance layer is configured to receive, through one of the at least two vias, a current applied to the test line.