公开(公告)号：US20250063729A1

公开(公告)日：2025-02-20

申请号：US18666514

申请日：2024-05-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junhyoung Kim ,  Joonyoung Kwon ,  Siwan Kim ,  Jiyoung Kim ,  Sukkang Sung

IPC: H10B41/35 ,  H01L23/00 ,  H01L25/18 ,  H10B12/00 ,  H10B41/41 ,  H10B43/35 ,  H10B43/40 ,  H10B80/00

Abstract: A semiconductor device includes a plate layer; conductive layers spaced apart from each other in a first direction perpendicular to an upper surface of the plate layer on the plate layer, extending by different lengths in a second direction perpendicular to the first direction, and forming a staircase region; a gap-fill insulating layer on the staircase region; and vertical structures penetrating through the gap-fill insulating layer and the conductive layers in the staircase region and extending in the first direction, and wherein the gap-fill insulating layer includes voids disposed symmetrically with respect to at least one of the vertical structures or a center of the staircase region in a third direction perpendicular to the first direction and the second direction.

公开(公告)号：US12096625B2

公开(公告)日：2024-09-17

申请号：US17375933

申请日：2021-07-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yoonjo Hwang ,  Jiyoung Kim ,  Jungtae Sung ,  Junyoung Choi

IPC: H10B41/27 ,  G11C5/02 ,  H01L23/522 ,  H01L23/528 ,  H10B43/27

CPC classification number: H10B41/27 ,  G11C5/025 ,  H01L23/5226 ,  H01L23/528 ,  H10B43/27

Abstract: A semiconductor device includes a first substrate structure including a first substrate, circuit devices, first interconnection lines, bonding metal layers on upper surfaces of the first interconnection lines, and a first bonding insulating layer on the upper surfaces of the first interconnection lines and on lateral surfaces of the bonding metal layers, and a second substrate structure on the first substrate structure, and including a second substrate, gate electrodes, channel structures, second interconnection lines, bonding vias connected to the second interconnection lines and the bonding metal layers and having a lateral surface that is inclined such that widths of the bonding vias increase approaching the first substrate structure, and a second bonding insulating layer in contact with at least lower portions of the bonding vias. The bonding metal layers include dummy bonding metal layers not connected to the bonding vias and that contacts the second bonding insulating layer.

公开(公告)号：US20240079323A1

公开(公告)日：2024-03-07

申请号：US18350999

申请日：2023-07-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joonyoung Kwon ,  Dawoon Jeong ,  Jiyoung Kim ,  Sukkang Sung ,  Woosung Yang

IPC: H01L23/528 ,  G11C5/06 ,  H01L25/065 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40 ,  H10B80/00

CPC classification number: H01L23/5283 ,  G11C5/063 ,  H01L25/0655 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40 ,  H10B80/00

Abstract: A semiconductor device includes a first conductive plate structure and a second conductive plate structure, arranged at a same vertical level on a semiconductor chip and horizontally spaced apart from each other on the semiconductor chip, a first structure on the first conductive plate structure and including first separation structures and first memory blocks, and a second structure on the second conductive plate structure and including second separation structures and second memory blocks. The first memory blocks are spaced apart from each other by the first separation structures, and extend in parallel to each other in a first horizontal direction. The second memory blocks are spaced apart from each other by the second separation structures, and extend in parallel to each other in a second horizontal direction. The first and second horizontal directions are parallel to an upper surface of the first conductive plate structure, and are perpendicular to each other.

公开(公告)号：US11853546B2

公开(公告)日：2023-12-26

申请号：US18163943

申请日：2023-02-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gijae Lee ,  Jebin Lee ,  Sunggu Kim ,  Jiyoung Kim ,  Daehee Cho ,  Hoon Choi ,  Bumryong Hong ,  Pilwon Seo ,  Jiwoo Lee

IPC: G06F3/04886 ,  G06F1/16

CPC classification number: G06F3/04886 ,  G06F1/1618 ,  G06F1/1643 ,  G06F1/1683

Abstract: At least one processor included in an electronic device can acquire first motion data about the motion of the electronic device through at least one motion sensor, acquire second motion data about a motion of an external device through a connector included in the electronic device, determine, on the basis of the first motion data and the second motion data, the folding angle between the electronic device and the external device connected to the electronic device, and determine, on the basis of the determined folding angle, an input mode that sets whether to display a user interface on a display or whether to block an input signal received through the connector. Various other embodiments identified through the specification are possible.

公开(公告)号：US11716854B2

公开(公告)日：2023-08-01

申请号：US17024105

申请日：2020-09-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jiyoung Kim ,  Woosung Yang ,  Sejie Takaki

IPC: H10B43/40 ,  G11C7/18 ,  H01L23/522 ,  H10B41/10 ,  H10B41/27 ,  H10B41/43 ,  H10B43/10 ,  H10B43/27

CPC classification number: H10B43/40 ,  G11C7/18 ,  H01L23/5226 ,  H10B41/10 ,  H10B41/27 ,  H10B41/43 ,  H10B43/10 ,  H10B43/27

Abstract: A 3D semiconductor memory device includes a peripheral circuit structure on a first substrate, a second substrate on the peripheral circuit structure, an electrode structure on the second substrate, the electrode structure comprising stacked electrodes, and a vertical channel structure penetrating the electrode structure. The peripheral circuit structure includes a dummy interconnection structure under the second substrate. The dummy interconnection structure includes stacked interconnection lines, and a via connecting a top surface of an uppermost one of the interconnection lines to a bottom surface of the second substrate.

公开(公告)号：US11569239B2

公开(公告)日：2023-01-31

申请号：US17126195

申请日：2020-12-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kiseok Lee ,  Bong-Soo Kim ,  Jiyoung Kim ,  Hui-Jung Kim ,  Seokhan Park ,  Hunkook Lee ,  Yoosang Hwang

IPC: H01L27/108 ,  H01L23/528 ,  H01L29/08 ,  H01L29/165 ,  H01L29/10 ,  H01L23/522 ,  H01L49/02

Abstract: Semiconductor memory devices may include first and second stacks on a substrate and first and second interconnection lines on the first and second stacks. Each of the first and second stacks may include semiconductor patterns vertically stacked on the substrate, conductive lines connected to the semiconductor patterns, respectively, and a gate electrode that is adjacent to the semiconductor patterns and extends in a vertical direction. The first stack may include a first conductive line and a first gate electrode, and the second stack may include a second conductive line and a second gate electrode. Lower surfaces of the first and second conductive lines may be coplanar. The first interconnection line may be electrically connected to at least one of the first and second conductive lines. The second interconnection line may be electrically connected to at least one of the first and second gate electrodes.

公开(公告)号：US10886375B2

公开(公告)日：2021-01-05

申请号：US16288910

申请日：2019-02-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongjin Lee ,  Junsoo Kim ,  Moonyoung Jeong ,  Satoru Yamada ,  Dongsoo Woo ,  Jiyoung Kim

IPC: H01L29/40 ,  H01L29/423 ,  H01L27/108 ,  H01L21/84 ,  H01L29/775 ,  H01L29/786 ,  H01L27/12 ,  H01L29/66 ,  B82Y10/00 ,  H01L27/088

Abstract: A semiconductor device may include a device isolation region configured to define an active region in a substrate, an active gate structure disposed in the active region, and a field gate structure disposed in the device isolation region. The field gate structure may include a gate conductive layer. The active gate structure may include an upper active gate structure including a gate conductive layer and a lower active gate structure formed under the upper active gate structure and vertically spaced apart from the upper active gate structure. The lower active gate structure may include a gate conductive layer. A top surface of the gate conductive layer of the field gate structure is located at a lower level than a bottom surface of the gate conductive layer of the upper active gate structure.

公开(公告)号：US10453796B2

公开(公告)日：2019-10-22

申请号：US15706655

申请日：2017-09-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jungwoo Song ,  Ye-Ro Lee ,  Kwangtae Hwang ,  Kwangmin Kim ,  Yong Kwan Kim ,  Jiyoung Kim

IPC: H01L27/108 ,  H01L21/768 ,  H01L23/532 ,  H01L27/02 ,  H01L23/522

Abstract: A semiconductor device including a substrate includes an active region. A bit line structure extends across the active region. A landing pad is disposed on an end portion of the active region. A first spacer is disposed between the bit line structure and the landing pad. A second spacer is disposed between the first spacer and the landing pad. An air spacer is disposed between the first spacer and the second spacer. A capping pattern is disposed between a sidewall of the landing pad and a sidewall of the bit line structure. The capping pattern defines a top surface of the air spacer and comprises a metallic material.

公开(公告)号：US20190043809A1

公开(公告)日：2019-02-07

申请号：US15909390

申请日：2018-03-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoonhee KANG ,  Jiyoung Kim ,  Taejin Yim ,  Jongmin Baek ,  Sanghoon Ahn ,  Hyeoksang Oh ,  Kyu-Hee Han

IPC: H01L23/532 ,  H01L21/768 ,  H01L21/02

CPC classification number: H01L23/53295 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02211 ,  H01L21/02216 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/02348 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76831 ,  H01L21/76834 ,  H01L23/5329

Abstract: Embodiments of the present inventive concepts provide methods of forming an ultra-low-k dielectric layer and the ultra-low-k dielectric layer formed thereby. The method may include forming a first layer by supplying a precursor including silicon, oxygen, carbon, and hydrogen, performing a first ultraviolet process on the first layer to convert the first layer into a second layer, and performing a second ultraviolet process on the second layer under a process condition different from that of the first ultraviolet process.

公开(公告)号：US20140159148A1

公开(公告)日：2014-06-12

申请号：US14097937

申请日：2013-12-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Woo Chung ,  Jiyoung Kim ,  Yoosang Hwang

IPC: H01L29/78

CPC classification number: H01L27/10814 ,  H01L27/10876 ,  H01L27/10891 ,  H01L27/10894

Abstract: A method of manufacturing a semiconductor device includes forming device isolation layer in a substrate to define active regions of which each has first regions and a second region between the first regions, forming a first trench and a pair of second trenches in the substrate, and forming gates in the second trenches, respectively. The first trench extends in a first direction and crosses the active regions and the device isolation layer. The second trenches are connected to a bottom of the first trench and extend in the first direction at both sides of the second regions.

Abstract translation: 一种制造半导体器件的方法包括在衬底中形成器件隔离层，以限定其中各具有第一区域的有源区和在第一区之间的第二区，在衬底中形成第一沟槽和一对第二沟槽， 分别在第二壕沟的大门。 第一沟槽沿第一方向延伸并与有源区和器件隔离层交叉。 第二沟槽连接到第一沟槽的底部并且在第二区域的两侧沿第一方向延伸。