中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

69 records (took 0.024 seconds)

    Semiconductor memory devices
    1.
    发明授权
    Semiconductor memory devices 有权

    公开(公告)号：US11569239B2

    公开(公告)日：2023-01-31

    申请号：US17126195

    申请日：2020-12-18

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kiseok Lee ,  Bong-Soo Kim ,  Jiyoung Kim ,  Hui-Jung Kim ,  Seokhan Park ,  Hunkook Lee ,  Yoosang Hwang

    IPC: H01L27/108 ,  H01L23/528 ,  H01L29/08 ,  H01L29/165 ,  H01L29/10 ,  H01L23/522 ,  H01L49/02

    Abstract: Semiconductor memory devices may include first and second stacks on a substrate and first and second interconnection lines on the first and second stacks. Each of the first and second stacks may include semiconductor patterns vertically stacked on the substrate, conductive lines connected to the semiconductor patterns, respectively, and a gate electrode that is adjacent to the semiconductor patterns and extends in a vertical direction. The first stack may include a first conductive line and a first gate electrode, and the second stack may include a second conductive line and a second gate electrode. Lower surfaces of the first and second conductive lines may be coplanar. The first interconnection line may be electrically connected to at least one of the first and second conductive lines. The second interconnection line may be electrically connected to at least one of the first and second gate electrodes.

    Semiconductor devices
    2.
    发明授权
    Semiconductor devices 有权

    公开(公告)号：US10720211B2

    公开(公告)日：2020-07-21

    申请号：US16458594

    申请日：2019-07-01

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sungwoo Kim ,  Bong-Soo Kim ,  Youngbae Kim ,  Kijae Hur ,  Gwanhyeob Koh ,  Hyeongsun Hong ,  Yoosang Hwang

    IPC: H01L27/00 ,  G11C14/00 ,  H01L27/24 ,  H01L23/528 ,  G11C13/00 ,  G11C5/02 ,  G11C11/00 ,  H01L45/00 ,  H01L27/108

    Abstract: A semiconductor device includes: a first memory section, a first peripheral circuit section, and a second peripheral circuit section that are disposed on a substrate; and a second memory section and a wiring section that are stacked on the second peripheral circuit section, wherein the first memory section includes a plurality of first memory cells, each of the first memory cells including a cell transistor and a capacitor connected to the cell transistor, the second memory section includes a plurality of second memory cells, each of the second memory cells including a variable resistance element and a select element coupled in series to each other, and the wiring section includes a plurality of line patterns, wherein the line patterns and the second memory cells are higher than the capacitor with respect to the substrate.

    Semiconductor device and method for fabricating the same
    3.
    发明授权
    Semiconductor device and method for fabricating the same 有权

    公开(公告)号：US10573652B2

    公开(公告)日：2020-02-25

    申请号：US15945401

    申请日：2018-04-04

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Myeong-Dong Lee ,  Jun-Won Lee ,  Ki Seok Lee ,  Bong-Soo Kim ,  Seok Han Park ,  Sung Hee Han ,  Yoo Sang Hwang

    IPC: H01L27/108 ,  H01L23/532 ,  H01L23/522 ,  H01L23/528

    Abstract: A semiconductor device includes a substrate having a trench, a bit line in the trench, a first spacer extending along the trench and at least a portion of a side surface of the bit line and in contact with the bit line, and a second spacer disposed within the trench on the first spacer. The bit line is narrower than the trench, and the first spacer includes silicon oxide. A method of forming a semiconductor device includes forming a trench in a substrate, forming a bit line within the first trench of width less than that of the first trench, and forming a first spacer that lines a portion of the trench and includes silicon oxide in contact with at least a portion of a side surface of the bit line, and forming a second spacer over the first spacer in the trench.

    Semiconductor memory devices
    9.
    发明授权
    Semiconductor memory devices 有权

    公开(公告)号：US11616065B2

    公开(公告)日：2023-03-28

    申请号：US17090419

    申请日：2020-11-05

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jiyoung Kim ,  Kiseok Lee ,  Bong-Soo Kim ,  Junsoo Kim ,  Dongsoo Woo ,  Kyupil Lee ,  HyeongSun Hong ,  Yoosang Hwang

    IPC: H01L27/108 ,  H01L27/06 ,  H01L49/02

    Abstract: Semiconductor memory devices are provided. A semiconductor memory device includes a substrate. The semiconductor memory device includes a plurality of memory cell transistors vertically stacked on the substrate. The semiconductor memory device includes a first conductive line connected to a source region of at least one of the plurality of memory cell transistors. The semiconductor memory device includes a second conductive line connected to a plurality of gate electrodes of the plurality of memory cell transistors. Moreover, the semiconductor memory device includes a data storage element connected to a drain region of the at least one of the plurality of memory cell transistors.

    Semiconductor memory device
    10.
    发明授权
    Semiconductor memory device 有权

    公开(公告)号：US11521977B2

    公开(公告)日：2022-12-06

    申请号：US17471824

    申请日：2021-09-10

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kiseok Lee ,  Chan-Sic Yoon ,  Augustin Hong ,  Keunnam Kim ,  Dongoh Kim ,  Bong-Soo Kim ,  Jemin Park ,  Hoin Lee ,  Sungho Jang ,  Kiwook Jung ,  Yoosang Hwang

    IPC: H01L27/108 ,  H01L27/24 ,  H01L27/22

    Abstract: A method of manufacturing a semiconductor memory device and a semiconductor memory device, the method including providing a substrate that includes a cell array region and a peripheral circuit region; forming a mask pattern that covers the cell array region and exposes the peripheral circuit region; growing a semiconductor layer on the peripheral circuit region exposed by the mask pattern such that the semiconductor layer has a different lattice constant from the substrate; forming a buffer layer that covers the cell array region and exposes the semiconductor layer; forming a conductive layer that covers the buffer layer and the semiconductor layer; and patterning the conductive layer to form conductive lines on the cell array region and to form a gate electrode on the peripheral circuit region.

Patent Agency Ranking