公开(公告)号：US20230089399A1

公开(公告)日：2023-03-23

申请号：US17719721

申请日：2022-04-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Solji SONG ,  Junyun Kweon ,  Jumyong Park ,  Dongjoon Oh ,  Chungsun Lee ,  Hyunsu Hwang

IPC: H01L23/528 ,  H01L23/532 ,  H01L21/78 ,  H01L23/498 ,  H01L25/00 ,  H01L25/065 ,  H01L23/00 ,  H01L23/16

Abstract: A semiconductor device includes a substrate, an insulating layer on a bottom surface of the substrate, a portion of a top surface of the insulating layer that faces the substrate being exposed outside a side surface of the substrate, a through via penetrating the substrate, an interconnection structure in the insulating layer, and a dummy pattern on the portion of the top surface of the insulating layer that is exposed by the substrate.

公开(公告)号：US20210343634A1

公开(公告)日：2021-11-04

申请号：US17099929

申请日：2020-11-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ju-Il CHOI ,  Jumyong Park ,  Jin Ho An ,  Chungsun Lee ,  Teahwa Jeong ,  Jeonggi Jin

IPC: H01L23/498 ,  H01L25/10 ,  H01L25/065 ,  H01L23/31

Abstract: An interconnection structure includes a dielectric layer, and a wiring pattern in the dielectric layer. The wiring pattern includes a via body, a first pad body that vertically overlaps the via body, and a line body that extends from the first pad body. The via body, the first pad body, and the line body are integrally connected to each other, and a level of a bottom surface of the first pad body is lower than a level of a bottom surface of the line body.

公开(公告)号：US09070748B2

公开(公告)日：2015-06-30

申请号：US14108771

申请日：2013-12-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Pil-Kyu Kang ,  Taeyeong Kim ,  Byung Lyul Park ,  Jumyong Park ,  Jinho Park ,  Kyu-Ha Lee ,  Deok-Young Jung ,  Gilheyun Choi

IPC: H01L21/768

CPC classification number: H01L25/0657 ,  G11C8/00 ,  G11C16/08 ,  H01L21/6835 ,  H01L21/7684 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/3192 ,  H01L23/481 ,  H01L23/544 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2223/54426 ,  H01L2223/54473 ,  H01L2224/02372 ,  H01L2224/03002 ,  H01L2224/03614 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/11002 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/1191 ,  H01L2224/13 ,  H01L2224/13024 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13169 ,  H01L2224/14051 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06565 ,  H01L2225/06593 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A conductive via of a semiconductor device is provided extending in a vertical direction through a substrate, a first end of the conductive via extending through a first surface of the substrate, so that the first end protrudes in the vertical direction relative to the first surface of the substrate. An insulating layer is provided on the first end of the conductive via and on the first surface of the substrate. An upper portion of a mask layer pattern is removed so that a capping portion of the insulating layer that is on the first end of the conductive via is exposed. A portion of the insulating layer at a side of, and spaced apart from, the conductive via, is removed, to form a recess in the insulating layer. The capping portion of the insulating layer on the first end of the conductive via is simultaneously removed.

Abstract translation: 提供半导体器件的导电通孔，其沿垂直方向穿过衬底延伸，导电通孔的第一端延伸穿过衬底的第一表面，使得第一端相对于衬底的第一表面在垂直方向上突出 底物。 绝缘层设置在导电通孔的第一端和基板的第一表面上。 除去掩模层图案的上部，使得在导电通孔的第一端上的绝缘层的封盖部分露出。 去除绝缘层的与导电通孔相隔一定距离的一部分，以在绝缘层中形成凹陷。 同时去除导电通孔第一端上的绝缘层的封盖部分。

公开(公告)号：US20250014958A1

公开(公告)日：2025-01-09

申请号：US18892965

申请日：2024-09-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeonggi Jin ,  Jumyong Park ,  Jinho An ,  Taehwa Jeong ,  Jinho Chun ,  Juil Choi ,  Atsushi Fujisaki

IPC: H01L23/31 ,  H01L23/29 ,  H01L23/522

Abstract: A semiconductor package includes: a lower package including a lower semiconductor chip, a molding layer on a side surface of the lower semiconductor chip, a conductive post in the molding layer and having a concave top surface, a lower redistribution pattern electrically connecting the lower semiconductor chip to the conductive post, and an upper redistribution electrically connected the conductive post; and an upper package on the lower package, the upper package including an upper semiconductor chip. A first portion of an inner wall of the molding layer contacts a sidewall of the conductive post, and a second portion of the inner wall of the molding layer extends vertically above the top surface of the conductive post, wherein the first and second portions of the inner wall of the molding layer are vertically coplanar with each other and with the sidewall of the conductive post.

公开(公告)号：US20240321794A1

公开(公告)日：2024-09-26

申请号：US18679806

申请日：2024-05-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeonggi Jin ,  Gyuho Kang ,  Unbyoung Kang ,  Heewon Kim ,  Jumyong Park ,  Hyunsu Hwang

IPC: H01L23/00 ,  H01L23/48 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L24/08 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/53238 ,  H01L24/05 ,  H01L2224/02251 ,  H01L2224/05009 ,  H01L2224/05555 ,  H01L2224/05647 ,  H01L2224/08146

Abstract: A semiconductor chip includes: a semiconductor substrate; a pad insulating layer on the semiconductor substrate; a through electrode which penetrates the semiconductor substrate and the pad insulating layer and includes a conductive plug and a conductive barrier layer surrounding a sidewall of the conductive plug; and a bonding pad which surrounds a sidewall of the through electrode and is spaced apart from the conductive plug with the conductive barrier layer disposed therebetween.

公开(公告)号：US20240234103A1

公开(公告)日：2024-07-11

申请号：US18404423

申请日：2024-01-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunsu Hwang ,  Unbyoung Kang ,  Jumyong Park ,  Dongjoon Oh ,  Hyunchul Jung ,  Sanghoo Cho

IPC: H01J37/32

CPC classification number: H01J37/32642 ,  H01J37/32715 ,  H01J2237/334

Abstract: A ring assembly is used in a semiconductor wafer etching device in which a plasma gas flow stream line is not uniform and which surrounds a wafer support plate supporting a semiconductor wafer. The ring assembly includes: an edge ring protruding from at least one side of the semiconductor wafer to have an upper surface higher than an upper surface of the semiconductor wafer; and a shadow ring movable up and down above the edge ring and configured to be tilted with respect to the semiconductor wafer.

公开(公告)号：US12021034B2

公开(公告)日：2024-06-25

申请号：US17198359

申请日：2021-03-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Solji Song ,  Byeongchan Kim ,  Jumyong Park ,  Jinho An ,  Chungsun Lee ,  Jeonggi Jin ,  Juil Choi

IPC: H01L23/538 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/5386 ,  H01L23/5383 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/16227

Abstract: A semiconductor package includes an interposer having a first surface and a second surface opposite to the first surface and including a plurality of bonding pads, and first and second semiconductor devices on the interposer. Each of the plurality of bonding pads includes a first pad pattern provided to be exposed from the first surface and having a first width and a second pad pattern provided on the first pad pattern and having a second width greater than the first width.

公开(公告)号：US20240203888A1

公开(公告)日：2024-06-20

申请号：US18430066

申请日：2024-02-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunsu Hwang ,  Junyun Kweon ,  Jumyong Park ,  Jin Ho An ,  Dongjoon Oh ,  Chungsun Lee ,  Ju-il Choi

IPC: H01L23/538 ,  H01L21/48 ,  H01L25/065 ,  H01L25/10

CPC classification number: H01L23/5383 ,  H01L21/4857 ,  H01L23/5386 ,  H01L25/0652 ,  H01L25/105 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058

Abstract: Disclosed are semiconductor packages and methods of fabricating the same. The semiconductor package includes a redistribution substrate including redistribution line patterns in a dielectric layer, and a semiconductor chip on the redistribution substrate. The semiconductor chip includes chip pads electrically connected to the redistribution line patterns. Each of the redistribution line patterns has a substantially planar top surface and a nonplanar bottom surface. Each of the redistribution line patterns includes a central portion and edge portions on opposite sides of the central portion. Each of the redistribution line patterns has a first thickness as a minimum thickness at the central portion and a second thickness as a maximum thickness at the edge portions.

公开(公告)号：US20240105680A1

公开(公告)日：2024-03-28

申请号：US18198418

申请日：2023-05-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junyoung Oh ,  Jumyong Park ,  Dongjoon Oh

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L25/0657 ,  H01L23/3107 ,  H01L23/49827 ,  H01L24/08 ,  H01L24/16 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/08146 ,  H01L2224/16225 ,  H01L2224/48147 ,  H01L2224/48149 ,  H01L2224/73257 ,  H01L2225/06506 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/15321

Abstract: A semiconductor chip stack structure includes: a first semiconductor chip including a first semiconductor substrate, a first redistribution layer on the first semiconductor substrate and including a first redistribution pattern, and a first pad on an outermost side of the first redistribution layer; a second semiconductor chip including a second semiconductor substrate, a second redistribution layer on the second semiconductor substrate and including a second redistribution pattern, and a second pad on an outermost side of the second redistribution layer, and an area of the second semiconductor chip being smaller than an area of the first semiconductor chip; a first metal wire on the first semiconductor chip; a second metal wire on the second semiconductor chip; and a molding member on the first semiconductor chip and at least a portion of each of the second semiconductor chip, the first metal wire, and the second metal wire.

公开(公告)号：US12199056B2

公开(公告)日：2025-01-14

申请号：US17726363

申请日：2022-04-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jumyong Park ,  Unbyoung Kang ,  Byeongchan Kim ,  Solji Song ,  Chungsun Lee

IPC: H01L23/48 ,  H01L23/00 ,  H01L25/065

Abstract: A semiconductor package includes a first semiconductor chip having a first substrate, a first insulating layer on the first substrate, and a plurality of first bonding pads on the first insulating layer, and having a flat upper surface by an upper surface of the first insulating layer and upper surfaces of the plurality of first bonding pads; and a second semiconductor chip on the upper surface of the first semiconductor chip and having a second substrate, a second insulating layer below the second substrate and in contact with the first insulating layer, and a plurality of second bonding pads on the second insulating layer and in contact with the first bonding pads, respectively, wherein the first insulating layer includes an insulating interfacial layer in contact with the second insulating layer, embedded in the first insulating layer, and spaced apart from the plurality of first bonding pads.