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    Semiconductor memory device compensating difference of bitline interconnection resistance
    11.
    发明授权
    Semiconductor memory device compensating difference of bitline interconnection resistance 有权
    半导体存储器件补偿位线互连电阻的差异

    公开(公告)号：US09595315B2

    公开(公告)日：2017-03-14

    申请号：US14734315

    申请日：2015-06-09

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Joon Han ,  Won-Kyung Park ,  Junhee Lim ,  Sungho Jang

    IPC: G11C11/4091 ,  G11C5/02 ,  G11C11/4094

    CPC classification number: G11C11/4091 ,  G11C5/02 ,  G11C11/4094 ,  G11C2207/002

    Abstract: A semiconductor memory device includes a bit line sense amplifier, a first column select gate, and a second column select gate. The bit line sense amplifier senses an electric potential difference between a bit line and a complementary bit line during a sensing operation for memory cells. The first column select gate transfers an electric potential on the bit line to a local sense amplifier based on a column select signal. The second column select gate transfers an electric potential on the complementary bit line to the local sense amplifier based on the column select signal. The first and second column select gates have different current drive abilities to compensate a difference in bit line interconnection resistance.

    Abstract translation: 半导体存储器件包括位线读出放大器，第一列选择栅极和第二列选择栅极。 在存储器单元的感测操作期间，位线读出放大器感测位线和互补位线之间的电位差。 第一列选择栅极基于列选择信号将位线上的电位传送到本地读出放大器。 第二列选择栅极基于列选择信号将互补位线上的电位传送到本地读出放大器。 第一和第二列选择栅极具有不同的电流驱动能力，以补偿位线互连电阻的差异。

    Three-dimensional semiconductor memory devices
    15.
    发明授权
    Three-dimensional semiconductor memory devices 有权

    公开(公告)号：US10790358B2

    公开(公告)日：2020-09-29

    申请号：US16515412

    申请日：2019-07-18

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Moorym Choi ,  Bongyong Lee ,  Junhee Lim

    IPC: H01L27/00 ,  H01L29/10 ,  H01L29/78 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582

    Abstract: A three-dimensional semiconductor memory device includes common source regions, an electrode structure between the common source regions, first channel structures penetrating the electrode structure, and second channel structures between the first channel structures and penetrating the electrode structures. The electrode structure includes electrodes vertically stacked on a substrate. The first channel structures include a first semiconductor pattern and a first vertical insulation layer. The second channel structures include a second vertical insulation layer surrounding a second semiconductor pattern. The second vertical insulation layer has a bottom surface lower than a bottom surface of the first vertical insulation layer.

    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES AND METHODS OF OPERATING THE SAME
    16.
    发明申请
    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES AND METHODS OF OPERATING THE SAME 审中-公开

    公开(公告)号：US20200303410A1

    公开(公告)日：2020-09-24

    申请号：US16714941

    申请日：2019-12-16

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kohji Kanamori ,  Yongseok Kim ,  Kyunghwan Lee ,  Junhee Lim

    IPC: H01L27/11582 ,  G11C16/04 ,  H01L27/11565 ,  H01L27/11573

    Abstract: Three-dimensional semiconductor memory devices are provided. A three-dimensional semiconductor memory device includes a plurality of word line blocks including a plurality of cell strings that are connected in parallel between a bit line and a common source line. Each of the cell strings includes a plurality of memory cell transistors that are stacked on a substrate in a vertical direction, a plurality of ground selection transistors that are connected in series between the plurality of memory cell transistors and the substrate, and a string selection transistor that is between the plurality of memory cell transistors and the bit line. In each of the cell strings, at least one of the plurality of ground selection transistors has a first threshold voltage, and remaining ones of the ground selection transistors have a second threshold voltage different from the first threshold voltage. Related methods of operating three-dimensional semiconductor memory devices are also provided.

    SEMICONDUCTOR DEVICES
    20.
    发明申请
    SEMICONDUCTOR DEVICES 有权

    公开(公告)号：US20250024677A1

    公开(公告)日：2025-01-16

    申请号：US18660638

    申请日：2024-05-10

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kang Lib Kim ,  Sungsu Moon ,  Seahoon Lee ,  Junhee Lim

    IPC: H10B43/27 ,  H10B43/35 ,  H10B43/40

    Abstract: A semiconductor device includes a gate electrode structure, a memory channel structure, and first and second contact plugs. The gate electrode structure includes gate electrodes spaced apart from each other in a first direction, and each of the gate electrodes extends in a second direction. The gate electrode structure has a staircase shape including step layers each of which includes two gate electrodes. The memory channel structure extends through the gate electrode structure. The first contact plug contacts an upper surface of a first gate electrode of the two gate electrodes at an upper level in a corresponding step layer. The second contact plug contacts a sidewall of a second gate electrode of the two gate electrodes at a lower level in the corresponding step layer. The second contact plug extends in the first direction and is electrically insulated from gate electrodes disposed below the second gate electrode.

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