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公开(公告)号：US11735214B2
公开(公告)日：2023-08-22
申请号：US17890580
申请日：2022-08-18
Applicant: Seagate Technology LLC
Inventor： Jason Bellorado , Marcus Marrow , Zheng Wu
CPC classification number: G11B5/59616 , G11B5/012
Abstract: Systems and methods are disclosed for synchronous writing of a grain patterned medium. The systems and methods can be implemented within a data storage device having a grain patterned medium. Further, a calibration process to determine a count of bits between servo wedges can be implemented in manufacturing, within the data storage device, or both. In some examples, the data storage device, during operation, can utilize the count of bits to perform synchronous writing, determine write errors, or both. Further, the servo wedge of the grain patterned medium may be patterned with a same or similar grain pattern as the data area that follows the servo wedge. Such a data storage device can implement a single clock for reading a servo wedge and writing a data area.
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公开(公告)号：US11475912B1
公开(公告)日：2022-10-18
申请号：US17345759
申请日：2021-06-11
Applicant: Seagate Technology LLC
Inventor： Jason Bellorado , Marcus Marrow , Zheng Wu
Abstract: Systems and methods are disclosed for synchronous writing of a grain patterned medium. The systems and methods can be implemented within a data storage device having a grain patterned medium. Further, a calibration process to determine a count of bits between servo wedges can be implemented in manufacturing, within the data storage device, or both. In some examples, the data storage device, during operation, can utilize the count of bits to perform synchronous writing, determine write errors, or both. Further, the servo wedge of the grain patterned medium may be patterned with a same or similar grain pattern as the data area that follows the servo wedge. Such a data storage device can implement a single clock for reading a servo wedge and writing a data area.
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公开(公告)号：US20220246171A1
公开(公告)日：2022-08-04
申请号：US17162218
申请日：2021-01-29
Applicant: Seagate Technology LLC
Inventor： Jason Bellorado , Marcus Marrow , Zheng Wu
Abstract: Systems and methods are disclosed for magnetoresistive asymmetry compensation using a hybrid analog and digital compensation scheme. In certain embodiments, a method may comprise receiving an analog signal at a continuous-time front end (CTFE) circuit, and performing, via the CTFE circuit, first magnetoresistive asymmetry (MRA) compensation on the analog signal to adjust the dynamic range of the analog signal based on an input range of an analog-to-digital converter (ADC). The method may further comprise converting the analog signal to a digital sample sequence via the ADC, and performing, via a digital MRA compensation circuit, second MRA compensation to correct residual MRA in the digital sample sequence. Offset compensation may also be performed in both the analog and digital domains.
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公开(公告)号：US11265000B1
公开(公告)日：2022-03-01
申请号：US17162411
申请日：2021-01-29
Applicant: Seagate Technology LLC
Inventor： Jason Bellorado , Marcus Marrow , Zheng Wu
Abstract: Systems and methods are disclosed for magnetoresistive asymmetry (MRA) compensation using a digital compensation scheme. In certain embodiments, a method may comprise receiving an analog signal at a continuous-time front end (CTFE) circuit, and performing analog offset compensation to constrain an extremum of the analog signal to adjust a dynamic range based on an input range of an analog-to-digital converter (ADC), rather than to modify the analog signal to have a zero mean. The method may further comprise converting the analog signal to a digital sample sequence via the ADC; performing, via a digital MRA compensation circuit, digital MRA compensation on the digital sample sequence; receiving, via a digital backend (DBE) subsystem, the digital sample sequence prior to digital MRA compensation; and generating, via a DBE, a bit sequence corresponding to the analog signal based on an output of the DBE subsystem and an output of the digital MRA compensation circuit.
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公开(公告)号：US11121729B1
公开(公告)日：2021-09-14
申请号：US16944050
申请日：2020-07-30
Applicant: Seagate Technology LLC
Inventor： Deepak Sridhara , Jason Bellorado , Ara Patapoutian , Marcus Marrow
Abstract: An error recovery process provides for identifying a set of failed data blocks read from a storage medium during execution of a read command, populating sample buffers in a read channel with data of a first subset of the set of failed data blocks, and initiating an error recovery process on the data in the sample buffers. Responsive to successful recovery of one or more data blocks in the first subset, recovered data is released from the sample buffers and sample buffers locations previously-storing the recovered data are repopulated with data of a second subset of the set of failed data blocks. The error recovery process is then initiated on the data of the second subset of the failed data blocks while the error recovery process is ongoing with respect to data of the first subset of failed data blocks remaining in the sample buffers.
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Patent Agency Ranking
公开(公告)号：US10714134B2
公开(公告)日：2020-07-14
申请号：US15793870
申请日：2017-10-25
Applicant: Seagate Technology LLC
Inventor： Marcus Marrow , Jason Bellorado , Vincent Brendan Ashe , Rishi Ahuja
IPC: G11B5/00 , G11B5/596 , G11B20/10 , H04L25/03 , G06F13/10 , G06F13/42 , H03K5/131 , H03M1/00 , H03M13/41 , H03K5/135 , H03L7/07 , H03L7/081 , H03L7/091 , H03G3/20 , H03M1/12 , H04L7/00 , H03M13/29 , H04B1/7105 , H03K5/00 , H04L7/033
Abstract: An apparatus can include a circuit configured to process an input signal using a set of channel parameters. The circuit can produce, using a first adaptation algorithm, a first set of channel parameters for use by the circuit as the set of channel parameters in processing the input signal. The circuit can further approximate a second set of channel parameters of a second adaptation algorithm for use by the circuit as the set of channel parameters in processing the input signal based on the first set of channel parameters and a relationship between a third set of channel parameters generated using the first adaptation algorithm and a fourth set of channel parameters generated using the second adaptation algorithm. In addition, the circuit can perform the processing of the input signal using the second set of channel parameters as the set of channel parameters.
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公开(公告)号：US10460762B1
公开(公告)日：2019-10-29
申请号：US16121296
申请日：2018-09-04
Applicant: Seagate Technology LLC
Inventor： Zheng Wu , Jason Bellorado , Marcus Marrow , Vincent Brendan Ashe
Abstract: An apparatus may comprise a circuit configured to receive first underlying data corresponding to a first signal with a first rate and receive a second signal with a second rate corresponding to second underlying data. The circuit may interpolate the first underlying data to generate a plurality of interpolated signals, determine, for the first signal, a first channel pulse response shape with the first rate, and determine an interference component signal based on the plurality of interpolated signals and the first channel pulse response shape. The circuit may then cancel interference in the second signal using the interference component signal to generate a cleaned signal.
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公开(公告)号：US20180366149A1
公开(公告)日：2018-12-20
申请号：US15793864
申请日：2017-10-25
Applicant: Seagate Technology LLC
Inventor： Jason Bellorado , Marcus Marrow
CPC classification number: G11B20/10222 , G11B5/59633 , G11B5/59666 , G11B20/10037 , G11B20/10055 , G11B20/1024 , H03K5/131 , H04L7/0029
Abstract: An apparatus may include a first and second servo channels configured to output first and second position information to first and second writers, respectively, via a shared write path such that the first and second writers write first and second position information to first and second magnetic recording medium surfaces, respectively. In addition, the apparatus may include a controller configured to control the shared write path such that write access is changed between the first servo channel and second servo channel a plurality of times during a revolution of the first magnetic recording medium surface and second magnetic recording medium surface.
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公开(公告)号：US10068608B1
公开(公告)日：2018-09-04
申请号：US15723969
申请日：2017-10-03
Applicant: Seagate Technology LLC
Inventor： Marcus Marrow , Jason Bellorado , Zheng Wu
Abstract: Systems and methods are disclosed for applying multi-stage multiple input single output (MISO) circuits for fast adaptation. An apparatus may comprise a first reader and a second reader configured to simultaneously read from a single track of a data storage medium, a MISO circuit. The MISO circuit may include a first stage filter having a first number of taps and configured to filter signal samples received from the first reader and the second reader and produce first filtered samples. The MISO circuit may also include a second stage filter having a second number of taps greater than the first number, and be configured to receive the first filtered samples corresponding to the first reader and the second reader from the first filter stage, filter the first filtered samples to produce second filtered samples, and combine the second filtered samples to produce a combined sample output.
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公开(公告)号：US11900970B2
公开(公告)日：2024-02-13
申请号：US17162218
申请日：2021-01-29
Applicant: Seagate Technology LLC
Inventor： Jason Bellorado , Marcus Marrow , Zheng Wu
CPC classification number: G11B5/09 , G06F13/385 , H03M1/12 , G11B2005/0013
Abstract: Systems and methods are disclosed for magnetoresistive asymmetry compensation using a hybrid analog and digital compensation scheme. In certain embodiments, a method may comprise receiving an analog signal at a continuous-time front end (CTFE) circuit, and performing, via the CTFE circuit, first magnetoresistive asymmetry (MRA) compensation on the analog signal to adjust the dynamic range of the analog signal based on an input range of an analog-to-digital converter (ADC). The method may further comprise converting the analog signal to a digital sample sequence via the ADC, and performing, via a digital MRA compensation circuit, second MRA compensation to correct residual MRA in the digital sample sequence. Offset compensation may also be performed in both the analog and digital domains.
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