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公开(公告)号：US11016681B1
公开(公告)日：2021-05-25
申请号：US16051244
申请日：2018-07-31
Applicant: Seagate Technology LLC
Inventor： Marcus Marrow , Jason Bellorado , Vincent Brendan Ashe , Zheng Wu
Abstract: An apparatus may include a circuit configured to receive an input signal at an input and process the input signal using a set of channel parameters. The circuit may further determine an error metric for the processing of the input signal using the set of channel parameters, compare the error metric to a plurality of thresholds, and when the error metric matches one of the plurality of thresholds, adapt, using an adaptation algorithm, the set of channel parameters to produce an updated set of channel parameters for use by the circuit as the set of channel parameters in subsequent processing of the input signal, the adaptation of the set of channel parameters being based on a weight corresponding to the matching threshold of the plurality of thresholds.
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公开(公告)号：US10468060B1
公开(公告)日：2019-11-05
申请号：US16144659
申请日：2018-09-27
Applicant: Seagate Technology LLC
Inventor： Zheng Wu , Jason Bellorado , Marcus Marrow , Vincent Brendan Ashe
Abstract: An apparatus may comprise a circuit configured to receive first underlying data corresponding to a first signal and receive a second signal corresponding to second underlying data. The circuit may determine an interference component signal based on the first underlying data corresponding to the first signal and a first channel pulse response shape for the first signal, determine estimated decisions corresponding to the second signal based on the second signal, and determine an estimated signal based on the estimated decisions corresponding to the second signal and a second channel pulse response shape for the second signal. The circuit may then generate a remaining signal based on the estimated signal and the second signal, generate an error signal based on the interference component signal and the remaining signal, and adapt one or more parameters of the first channel pulse response shape based on the error signal.
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公开(公告)号：US10410672B1
公开(公告)日：2019-09-10
申请号：US16104933
申请日：2018-08-19
Applicant: Seagate Technology LLC
Inventor： Marcus Marrow , Jason Bellorado , Zheng Wu
Abstract: Systems and methods are disclosed for applying multi-stage multiple input single output (MISO) circuits for fast adaptation. An apparatus may comprise a first reader and a second reader configured to simultaneously read from a single track of a data storage medium, a MISO circuit. The MISO circuit may include a first stage filter having a first number of taps and configured to filter signal samples received from the first reader and the second reader and produce first filtered samples. The MISO circuit may also include a second stage filter having a second number of taps greater than the first number, and be configured to receive the first filtered samples corresponding to the first reader and the second reader from the first filter stage, filter the first filtered samples to produce second filtered samples, and combine the second filtered samples to produce a combined sample output.
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公开(公告)号：US20180366156A1
公开(公告)日：2018-12-20
申请号：US15722641
申请日：2017-10-02
Applicant: Seagate Technology LLC
Inventor： Marcus Marrow , Jason Bellorado , Zheng Wu
IPC: G11B20/10
Abstract: Systems and methods are disclosed for sampling signals in multi-reader magnetic recording. In certain embodiments, an apparatus may comprise a plurality of read heads configured to simultaneously read from a single track of a storage medium, a plurality of analog to digital converters (ADCs) configured to receive signal patterns from corresponding read heads, and a circuit configured to control the plurality of ADCs to sample the signal patterns according to a single clock signal generator. The output of the ADCs may be individually delayed based on a down-track offset of the read heads in order to align the samples, so that samples corresponding to the same portion of the recorded signal can be combined for bit pattern detection.
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公开(公告)号：US10084553B1
公开(公告)日：2018-09-25
申请号：US15389385
申请日：2016-12-22
Applicant: Seagate Technology LLC
Inventor： Jason Vincent Bellorado , Marcus Marrow , Zheng Wu
CPC classification number: H04L7/0332 , H04L1/00 , H04L7/0029 , H04L25/03057 , H04L25/03286 , H04L25/03318
Abstract: In certain embodiments, a method may include receiving one or more equalized samples of an input signal. The method may further include mitigating one or more excursions in the one or more equalized samples based on one or more current decisions of an iterative decoding process to generate compensated equalized samples. In addition, the method may include performing iterative decoding operations based on the compensated equalized samples, updating the current decisions of the iterative decoding process and outputting the current decisions as a converged result when the iterative decoding operations have converged for the compensated equalized samples.
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Patent Agency Ranking
公开(公告)号：US11735220B2
公开(公告)日：2023-08-22
申请号：US17562426
申请日：2021-12-27
Applicant: Seagate Technology LLC
Inventor： Zheng Wu , Jason Bellorado
IPC: G11B20/10 , G11B5/596 , G11B11/105
CPC classification number: G11B11/10578 , G11B5/59655
Abstract: Systems and methods are disclosed for phase locking of a clock. In some embodiments, a phase locked clock (PLC) module can phase-lock a write clock to a media written with multiple servo zones of different frequencies. In some implementations, this can be utilized to perform a self-servo write (SSW) of a disc surface within a hard disc drive (HDD). A PLC module can perform a method of writing with a single frequency phase coherently while a read element passes over servo zones with different frequencies. While the PLC module can perform such methods for a SSW process, the methods can also be utilized for other applications that can benefit from writing with a single frequency phase coherently based on servo zones with different frequencies.
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公开(公告)号：US20220247418A1
公开(公告)日：2022-08-04
申请号：US17582376
申请日：2022-01-24
Applicant: Seagate Technology LLC
Inventor： Jason Bellorado , Marcus Marrow , Zheng Wu
Abstract: Systems and methods are disclosed for magnetoresistive asymmetry (MRA) compensation using a digital compensation scheme. In certain embodiments, a method may comprise receiving an analog signal at a continuous-time front end (CTFE) circuit, and performing analog offset compensation to constrain an extremum of the analog signal to adjust a dynamic range based on an input range of an analog-to-digital converter (ADC), rather than to modify the analog signal to have a zero mean. The method may further comprise converting the analog signal to a digital sample sequence via the ADC; performing, via a digital MRA compensation circuit, digital MRA compensation on the digital sample sequence; receiving, via a digital backend (DBE) subsystem, the digital sample sequence prior to digital MRA compensation; and generating, via a DBE, a bit sequence corresponding to the analog signal based on an output of the DBE subsystem and an output of the digital MRA compensation circuit.
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公开(公告)号：US11018842B1
公开(公告)日：2021-05-25
申请号：US16051252
申请日：2018-07-31
Applicant: Seagate Technology LLC
Inventor： Jason Bellorado , Marcus Marrow , Zheng Wu
Abstract: An apparatus may include a sampling circuit configured to produce a sequence of input samples based on a continuous time input signal and a sample clock signal, the sampling phase of the sequence of input samples based on a phase control value output by a timing recovery circuit. In addition, the apparatus may include the timing recovery circuit configured to receive the sequence of input samples, detect, for a current sample of the sequence of input samples, a phase offset in the sampling phase of the sequence of input samples, the phase offset being a deviation of the sampling phase from an expected phase, and in response to detecting the phase offset, select a bandwidth for timing recovery. Further, the timing recovery circuit may generate an updated phase control value based on the selected bandwidth for timing recovery.
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公开(公告)号：US10755734B2
公开(公告)日：2020-08-25
申请号：US16570785
申请日：2019-09-13
Applicant: Seagate Technology LLC
Inventor： Jason Bellorado , Marcus Marrow , Zheng Wu
IPC: G11B5/596 , G11B20/10 , H04L25/03 , G06F13/10 , G06F13/42 , H03K5/131 , H03M1/00 , H03M13/41 , H03K5/135 , H03L7/07 , H03L7/081 , H03L7/091 , H03G3/20 , H03M1/12 , H04L7/00 , H03M13/29 , H04B1/7105 , H03K5/00 , H04L7/033
Abstract: An apparatus may include a circuit configured to receive first and second samples of an underlying data from respective first and second sample periods and which correspond to respective first and second sensors, a phase control value may have first and second values during respective first and second sample periods. The phase control value may be a control value for a sample clock signal. The circuit may also determine a difference in the phase control value between the first value and the second value. The circuit may then digitally interpolate the first and second samples to produce a phase shifted first and second samples where the digital interpolation of at least one of the first and second samples mat be at least in part based on the difference in the phase control value to compensate for a phase misalignment between the first sample and the second sample.
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公开(公告)号：US10665256B2
公开(公告)日：2020-05-26
申请号：US15791190
申请日：2017-10-23
Applicant: Seagate Technology LLC
Inventor： Jason Bellorado , Marcus Marrow , Zheng Wu
IPC: G11B5/596 , G11B20/10 , H04L25/03 , H03K5/131 , H03M1/00 , H03M13/41 , H03K5/135 , H03L7/07 , H03L7/081 , H03L7/091 , H04L7/00 , H03M13/29 , H04B1/7105 , H03K5/00 , H04L7/033
Abstract: An apparatus may include a circuit configured to receive a first phase control value of a phase control value signal, generate a first phase interpolator control signal value of a phase interpolator control signal and generate a first digital interpolator control signal value of a digital interpolator control signal. The apparatus may further be configured to phase interpolate a clock signal based on the first phase interpolator control signal value to produce a phase shifted clock signal and digitally interpolate a digital sample based on the first digital interpolator signal value to produce a phase shifted digital sample having an effective phase based on the first phase control value, the digital sample generated using the phase shifted clock signal as a sample clock.
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