中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

19 records (took 0.018 seconds)

    FIRMWARE UPDATE WITH LOGICAL ADDRESS REMAPPING
    11.
    发明申请
    FIRMWARE UPDATE WITH LOGICAL ADDRESS REMAPPING 有权

    公开(公告)号：US20240427588A1

    公开(公告)日：2024-12-26

    申请号：US18340993

    申请日：2023-06-26

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Yaron Alpert ,  Yoav Ben-Yehezkel ,  Barak Cherches

    IPC: G06F8/65

    Abstract: A system includes memory which has a first resource at a first physical address space that includes a first physical address, and a second resource at a second physical address space that includes a second physical address. A memory mapper is coupled to the memory. The memory mapper is configured to convert logical addresses to physical addresses. A processor is coupled to the memory mapper. The processor is configured to execute the first resource from a first logical address mapped by the memory mapper to the first physical address. While executing a firmware update resource, the processor can remap the first logical address to the second physical address using the memory mapper and then execute the second resource from the first logical address.

    Countermeasure against fault injection attacks
    12.
    发明授权
    Countermeasure against fault injection attacks 有权

    公开(公告)号：US12111931B2

    公开(公告)日：2024-10-08

    申请号：US17853612

    申请日：2022-06-29

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Uri Weinrib ,  Barak Cherches ,  Clive David Bittlestone

    IPC: G06F13/24 ,  G06F21/52 ,  G06F21/56

    CPC classification number: G06F21/566 ,  G06F21/52 ,  G06F2221/034

    Abstract: A method includes programming first and second values and a first compare enable command into respective first operand, second operand, and first compare enable command registers in a hardware comparator circuit. The method includes determining that a first match exists corresponding to the first and second values, programming a third value into the first operand register and a fourth value into the second operand register, and programming a second compare enable command into a second compare enable command register in the hardware comparator circuit. In response to a determination that a second match exists corresponding to the third and fourth values, the method includes asserting a success interrupt signal, programming a fifth value into the first operand register and a sixth value into the second operand register and programming a second compare enable command into a second compare enable command register in the hardware comparator circuit.

    ADDRESS SPACE MAPPING
    14.
    发明申请
    ADDRESS SPACE MAPPING 有权

    公开(公告)号：US20250086107A1

    公开(公告)日：2025-03-13

    申请号：US18463046

    申请日：2023-09-07

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Yaron Alpert ,  Barak Cherches ,  Guy Shubeli ,  Yoav Ben-Yehezkel

    IPC: G06F12/02 ,  G06F12/14

    Abstract: In an embodiment, a method includes receiving a logical address from a primary device and determining an address header based on the logical address. The method also includes determining an offset value based on the address header and applying the offset value to a first portion of the logical address to create an offset address portion. The method further includes generating a physical address that includes the address header and the offset address portion and accessing a physical resource using the physical address.

    HARDWARE SYSTEM FOR AUTOMATIC DIRECT MEMORY ACCESS DATA FORMATTING
    18.
    发明申请
    HARDWARE SYSTEM FOR AUTOMATIC DIRECT MEMORY ACCESS DATA FORMATTING 有权

    公开(公告)号：US20230112720A1

    公开(公告)日：2023-04-13

    申请号：US17499522

    申请日：2021-10-12

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Guy Shubeli ,  Barak Cherches ,  Uri Weinrib

    IPC: G06F3/06

    Abstract: A hardware direct memory access controller including an input port configured to receive data from an electronic device for direct memory access transfer, an output port configured to provide data for direct memory access, and processing circuitry is disclosed. The processing circuitry is configured to receive data comprising a header and payload from the electronic device via the input port, parse the header to determine data parameters including a transaction length and an input data format, and select a target destination for the data based at least in part on the data parameters. The processing circuitry is also configured to allocate memory within the target destination based at least in part on the transaction length, and to format the payload for direct memory access based at least in part on the data parameters, and to transfer the formatted payload for storage within the allocated memory within the target destination via the output port using direct memory access.

    Autonomous Sleep Mode
    19.
    发明申请
    Autonomous Sleep Mode 有权
    自主睡眠模式

    公开(公告)号：US20160041831A1

    公开(公告)日：2016-02-11

    申请号：US14452700

    申请日：2014-08-06

    Applicant: Texas Instruments Incorporated

    Inventor： Asaf Carmeli ,  Ben Gilboa ,  Avi Baum ,  Barak Cherches ,  Mukesh Kumar

    IPC: G06F9/44 ,  G06F13/16 ,  G06F1/32 ,  G06F13/28 ,  G06F13/42

    CPC classification number: G06F9/4418 ,  G06F1/3287 ,  G06F13/1673 ,  G06F13/28 ,  G06F13/4291 ,  Y02D10/14 ,  Y02D10/151

    Abstract: A system and method is disclosed that enables a peripheral or slave device to seamlessly transition in and out of sleep state while remaining completely transparent to host software. When the device is in a sleep mode and incoming data is detected, the device begins a wake-up procedure and data is routed to a first, transitional memory. The size of the transitional memory is selected such that it is capable of buffering data received during time required for the system memory to stabilize from wake-up. Once a second, extended memory is stabilized, the data is buffered from the transitional memory to the extended memory. The device resumes normal operation when its processor has initialized and can read data from the extended memory.

    Abstract translation: 公开了一种系统和方法，其使得外围设备或从设备无缝地转换进入和离开休眠状态，同时对主机软件保持完全透明。 当设备处于睡眠模式并且检测到传入数据时，设备开始唤醒过程，数据被路由到第一个过渡存储器。 选择过渡存储器的大小，使得其能够缓冲系统存储器在唤醒期间稳定所需的时间期间接收到的数据。 一旦一秒钟，扩展存储器就被稳定，数据就从缓冲存储器过渡到扩展存储器。 当处理器初始化并且可以从扩展内存读取数据时，该设备恢复正常操作。

Patent Agency Ranking