Abstract:
An electrostatic discharge (ESD) protection circuit (FIG. 2A) for an integrated circuit is disclosed. The circuit is formed on a substrate (P-EPI) having a first conductivity type. A buried layer (NBL 240) having a second conductivity type is formed below a face of the substrate. A first terminal (206) and a second terminal (204) are formed at a face of the substrate. A first ESD protection device (232) has a first current path between the first terminal and the buried layer. A second ESD protection device (216) has a second current path in series with the first current path and between the second terminal and the buried layer.
Abstract:
An integrated circuit with an embedded heat exchanger for coupling heat to an embedded thermoelectric device from a thermal source that is electrically isolated from a thermoelectric device. A method for forming an integrated circuit with an embedded heat exchanger.
Abstract:
An integrated circuit containing an embedded resistor in close proximity to an embedded thermoelectric device. An integrated circuit containing an embedded resistor in close proximity to an embedded thermoelectric device composed of thermoelectric elements and at least one switch to disconnect at least one thermoelectric element from the thermoelectric device. Methods for testing embedded thermoelectric devices.
Abstract:
An electrostatic discharge (ESD) protection circuit (FIG. 2A) for an integrated circuit is disclosed. The circuit is formed on a substrate (P-EPI) having a first conductivity type. A buried layer (NBL 240) having a second conductivity type is formed below a face of the substrate. A first terminal (206) and a second terminal (204) are formed at a face of the substrate. A first ESD protection device (232) has a first current path between the first terminal and the buried layer. A second ESD protection device (216) has a second current path in series with the first current path and between the second terminal and the buried layer.
Abstract:
An electrostatic discharge (ESD) protection circuit (FIG. 2A) for an integrated circuit is disclosed. The circuit is formed on a substrate (P-EPI) having a first conductivity type. A buried layer (NBL 240) having a second conductivity type is formed below a face of the substrate. A first terminal (206) and a second terminal (204) are formed at a face of the substrate. A first ESD protection device (232) has a first current path between the first terminal and the buried layer. A second ESD protection device (216) has a second current path in series with the first current path and between the second terminal and the buried layer.
Abstract:
An integrated circuit includes a first transistor array over a semiconductor substrate and is distributed among a first plurality of first transistor banks. A second transistor array in or over the semiconductor substrate is distributed among a second plurality of second transistor banks. A first one of the first transistor banks is located between a first one and a second one of the second transistor banks, and the second one of the second transistor banks is located between the first one of the first transistor banks and a second one of the first transistor banks. The first transistor array and the second transistor array may be alternately operated to implement a voltage-conversion integrated circuit.
Abstract:
An integrated circuit has thermoelectric cooling devices integrated into bondpads. A method for operating the integrated circuit includes turning a thermal switch to a thermoelectric cooler operate position when the integrated circuit is powered up, turning the thermal switch to a thermoelectric cooler operate position to allow the thermoelectric cooler to operate when the integrated circuit powers down, and turning the thermal switch to a thermoelectric cooler off position when a predetermined integrated circuit chip temperature is reached.
Abstract:
A circuit board includes an embedded thermoelectric device with hard thermal bonds. A method includes embedding a thermoelectric device in a circuit board and forming hard thermal bonds.
Abstract:
An electrostatic discharge (ESD) protection circuit (FIG. 3C) is disclosed. The circuit includes a bipolar transistor (304) having a base, collector, and emitter. Each of a plurality of diodes (308-316) has a first terminal coupled to the base and a second terminal coupled to the collector. The collector is connected to a first terminal (V+). The emitter is connected to a first power supply terminal (V−).
Abstract:
An electrostatic discharge (ESD) protection circuit (FIG. 3C) is disclosed. The circuit includes a bipolar transistor (304) having a base, collector, and emitter. Each of a plurality of diodes (308-316) has a first terminal coupled to the base and a second terminal coupled to the collector. The collector is connected to a first terminal (V+). The emitter is connected to a first power supply terminal (V−).