公开(公告)号：US20240427716A1

公开(公告)日：2024-12-26

申请号：US18816201

申请日：2024-08-27

Applicant: Texas Instruments Incorporated

Inventor： Niraj Nandan ,  Rajasekhar Reddy Allu ,  Brian Chae ,  Mihir Mody

IPC: G06F13/28 ,  G06F9/48 ,  G06F13/16 ,  G06F13/40

Abstract: Systems and methods enable data aggregation and pattern adaptation in hardware acceleration subsystems. In an example, a system, which may be a hardware thread scheduling system, includes schedulers, each associated with a pattern adapter; hardware accelerators respectively coupled to the schedulers; load store engines respectively associated with the hardware accelerators; a memory coupled to the load store engines; and a direct memory access (DMA) circuit coupled to the memory. Each pattern adapter is able to convert data from one format to another, and each load store engine is able to aggregate data elements to form larger data elements to improve overall processing efficiency.

公开(公告)号：US11947832B2

公开(公告)日：2024-04-02

申请号：US17668052

申请日：2022-02-09

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sriramakrishnan Govindarajan ,  Mihir Mody

IPC: G06F3/06 ,  G06F13/28

CPC classification number: G06F3/0656 ,  G06F3/0604 ,  G06F3/0679 ,  G06F13/28 ,  G06F2213/28

Abstract: An integrated circuit is presented. The integrated circuit has a set of sensor input interfaces and an output interface. The integrated circuit further has a memory with a first and second memory locations. The integrated circuit further has a multi-chip hub module which has a transaction buffer with both a real-time and a non-real-time buffer. The multi-chip hub module has a context mapper, a re-formatter module and an error handling module. The context mapper is configured to map data to the first or second memory location. The multi-chip hub module is configured to process data through the modules and provide processed data to the output interface.

公开(公告)号：US20240089425A1

公开(公告)日：2024-03-14

申请号：US18510884

申请日：2023-11-16

Applicant: Texas Instruments Incorporated

Inventor： Niraj Nandan ,  Brian Chae ,  Mihir Mody ,  Rajasekhar Reddy Allu

IPC: H04N17/00 ,  H04N5/14 ,  H04N7/18

CPC classification number: H04N17/004 ,  H04N5/144 ,  H04N7/183

Abstract: Devices, systems, and methods detect an image frame freeze condition. An example device includes a core logic circuit configured to generate statistics for received image data associated with an image frame, perform a census transform on pixel values of the image data to generate census transformed data, arrange the census transformed data into a binary string having a binary value, and generate transformed image data by replacing a select pixel value of the pixel values of the image data with a decimal value corresponding to the binary value; a load/store engine (LSE) coupled to the core logic circuit, the LSE configured to determine a cyclic redundancy check (CRC) value based on at least one of the image data, the transformed image data, and at least one statistic of the statistics; and an interface configured to transmit the CRC value to a host device.

公开(公告)号：US20240040266A1

公开(公告)日：2024-02-01

申请号：US18147964

申请日：2022-12-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Hrushikesh Garud ,  Rajasekhar Allu ,  Gang Hua ,  Jing-Fei Ren ,  Mayank Mangla ,  Niraj Nandan ,  Mihir Mody ,  Pandy Kalimuthu

IPC: H04N23/76 ,  H04N23/11 ,  H04N23/84 ,  H04N23/81

CPC classification number: H04N23/76 ,  H04N23/11 ,  H04N23/843 ,  H04N23/81 ,  H04N23/667

Abstract: A system is provided. The system generally includes a first processor configured to receive image input data from a red-green-blue infrared (RGBIR) sensor. The first processor of the system is configured to generate a first intermediate image data from the image input data. The system generally includes a second processor. The second processor of the system is configured to generate a second intermediate image data that includes red-green-blue (RGB) image data from the first intermediate image data, and to generate a third intermediate image data that includes infrared (IR) image data from the first intermediate image data. The system generally includes a third processor. The third processor of the system is configured to process the third intermediate image data. The system generally includes a fourth processor. The fourth processor of the system is configured to process the second image data.

公开(公告)号：US11586465B2

公开(公告)日：2023-02-21

申请号：US17138649

申请日：2020-12-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Niraj Nandan ,  Mihir Mody

IPC: G06F9/48 ,  G06F9/30 ,  G06F9/38 ,  G06F9/54

Abstract: A device includes a hardware data processing node configured to execute a respective task, and a hardware thread scheduler including a hardware task scheduler. The hardware task scheduler is coupled to the hardware data processing node and has a producer socket, a consumer socket, and a spare socket. The spare socket is configured to provide data control signals also provided by a first socket of the producer and consumer sockets responsive to a memory-mapped register being a first value. The spare socket is configured to provide data control signals also provided by a second socket of the producer and consumer sockets responsive to the memory-mapped register being a second value.

公开(公告)号：US11163861B2

公开(公告)日：2021-11-02

申请号：US16188560

申请日：2018-11-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Deepak Kumar Poddar ,  Mihir Mody ,  Veeramanikandan Raju ,  Jason A. T. Jones

IPC: G06F21/00 ,  G06F21/16 ,  G06N3/04 ,  G06N20/00 ,  G06F21/12

Abstract: In some examples, a system includes storage storing a machine learning model, wherein the machine learning model comprises a plurality of layers comprising multiple weights. The system also includes a processing unit coupled to the storage and operable to group the weights in each layer into a plurality of partitions; determine a number of least significant bits to be used for watermarking in each of the plurality of partitions; insert one or more watermark bits into the determined least significant bits for each of the plurality of partitions; and scramble one or more of the weight bits to produce watermarked and scrambled weights. The system also includes an output device to provide the watermarked and scrambled weights to another device.

公开(公告)号：US20210326229A1

公开(公告)日：2021-10-21

申请号：US17135481

申请日：2020-12-28

Applicant: Texas Instruments Incorporated

Inventor： Rajat Sagar ,  Niraj Nandan ,  Kedar Chitnis ,  Brijesh Jadav ,  Mihir Mody

IPC: G06F11/30 ,  G06F11/07 ,  G06F15/78

Abstract: Methods, apparatus, systems and articles of manufacture for an example event processor are disclosed to retrieve an input event and an input event timestamp corresponding to the input event, generate an output event based on the input event and the input event timestamp, in response to determination that an input event threshold is exceeded within a threshold of time, and an anomaly detector to retrieve the output event, determine whether the output event indicates threat to functional safety of a system on a chip, and in response to determining the output event indicates threat to functional safety of the system on a chip, adapt a process for the system on a chip to preserve functional safety.

公开(公告)号：US20210209041A1

公开(公告)日：2021-07-08

申请号：US17139970

申请日：2020-12-31

Applicant: Texas Instruments Incorporated

Inventor： Niraj Nandan ,  Rajasekhar Reddy Allu ,  Brian Chae ,  Mihir Mody

IPC: G06F13/28 ,  G06F9/48 ,  G06F13/40 ,  G06F13/16

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed herein to enable data aggregation and pattern adaptation in hardware acceleration subsystems. In some examples, a hardware acceleration subsystem includes a first scheduler, a first hardware accelerator coupled to the first scheduler to process at least a first data element and a second data element, and a first load store engine coupled to the first hardware accelerator, the first load store engine configured to communicate with the first scheduler at a superblock level by sending a done signal to the first scheduler in response to determining that a block count is equal to a first BPR value and aggregate the first data element and the second data element based on the first BPR value to generate a first aggregated data element.

公开(公告)号：US10767998B2

公开(公告)日：2020-09-08

申请号：US16114419

申请日：2018-08-28

Applicant: Texas Instruments Incorporated

Inventor： Rahul Gulati ,  Aishwarya Dubey ,  Nainala Vyagrheswarudu ,  Vasant Easwaran ,  Prashant Dinkar Karandikar ,  Mihir Mody

IPC: G01C21/20 ,  G06F11/10

Abstract: Information communication circuitry, including a first integrated circuit for coupling to a second integrated circuit in a package on package configuration. The first integrated circuit comprises processing circuitry for communicating information bits, and the information bits comprise data bits and error correction bits, where the error correction bits are for indicating whether data bits are received correctly. The second integrated circuit comprises a memory for receiving and storing at least some of the information bits. The information communication circuitry also includes interfacing circuitry for selectively communicating, along a number of conductors, between the package on package configuration. In a first instance, the interfacing circuitry selectively communicates only data bits along the number of conductors. In a second instance, the interfacing circuitry selectively communicates data bits along a first set of the number of conductors and error correction bits along a second set of the number of conductors.

公开(公告)号：US20250168520A1

公开(公告)日：2025-05-22

申请号：US19027193

申请日：2025-01-17

Applicant: Texas Instruments Incorporated

Inventor： Niraj Nandan ,  Mihir Mody ,  Rajasekhar Allu ,  Manoj Koul ,  Pandy Kalimuthu ,  David Stoller

IPC: H04N23/81 ,  H04N23/84 ,  H04N23/88

Abstract: In described examples, an integrated circuit includes first, second, third, and fourth image processing blocks, a data selection circuitry, and a pipeline memory. An input of the first image processing block receives raw image data. An input of the second image processing block is coupled to an output of the first image processing block. An input of the third image processing block is coupled to an output of the second image processing block. A first input of the data selection circuitry is coupled to an output of the first image processing block, and a second input of the data selection circuitry is coupled to an output of the second image processing block. A data input of the pipeline memory is coupled to an output of the data selection circuitry, and an output of the pipeline memory is coupled to an input of the fourth image processing block.