公开(公告)号：US20200335349A1

公开(公告)日：2020-10-22

申请号：US16889448

申请日：2020-06-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Siao-Shan Wang ,  Cheng-Han Wu ,  Ching-Yu Chang ,  Chin-Hsiang LIN

IPC: H01L21/308 ,  H01L21/027 ,  G03F7/40 ,  G03F7/26

Abstract: Provided is a material composition and method that includes forming a patterned resist layer on a substrate, where the patterned resist layer has a first line width roughness. In various embodiments, the patterned resist layer is coated with a treatment material, where a first portion of the treatment material bonds to surfaces of the patterned resist layer. In some embodiments, a second portion of the treatment material (e.g., not bonded to surfaces of the patterned resist layer) is removed, thereby providing a treated patterned resist layer, where the treated patterned resist layer has a second line width roughness less than the first line width roughness.

公开(公告)号：US10720362B2

公开(公告)日：2020-07-21

申请号：US16221740

申请日：2018-12-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuei-Ming Chang ,  Rei-Jay Hsieh ,  Cheng-Han Wu ,  Chie-Iuan Lin

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L21/762 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234

Abstract: A device includes a semiconductor fin, a first source/drain feature, a second source/drain feature, and a dielectric plug. The first source/drain feature adjoins the semiconductor fin. The second source/drain feature adjoins the semiconductor fin. The dielectric plug extends from above the semiconductor fin into the semiconductor fin, the dielectric plug is between the first source/drain feature and the second source/drain feature. The dielectric plug includes a waist and a first portion below the waist, and a width of the waist is less than a width of the first portion of the dielectric plug.

公开(公告)号：US20180348639A1

公开(公告)日：2018-12-06

申请号：US15608631

申请日：2017-05-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Yu Liu ,  Ya-Ching Chang ,  Cheng-Han Wu ,  Ching-Yu Chang ,  Chin-Hsiang Lin

IPC: G03F7/20 ,  G03F7/039 ,  G03F7/038 ,  G03F7/004 ,  G03F7/26 ,  G03F7/40

Abstract: The present disclosure provides a method for lithography patterning in accordance with some embodiments. The method includes forming a resist layer over a substrate and performing an exposing process to the resist layer. The resist layer includes a polymer backbone, an acid labile group (ALG) bonded to the polymer backbone, a sensitizer bonded to the polymer backbone, a photo-acid generator (PAG), and a thermo-base generator (TBG). The method further includes baking the resist layer at a first temperature and subsequently at a second temperature. The second temperature is higher than the first temperature. The method further includes developing the resist layer in a developer, thereby forming a patterned resist layer.

公开(公告)号：US20240249981A1

公开(公告)日：2024-07-25

申请号：US18594735

申请日：2024-03-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuei-Ming Chang ,  Rei-Jay Hsieh ,  Cheng-Han Wu ,  Chie-luan Lin

IPC: H01L21/8238 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823878 ,  H01L21/76232 ,  H01L21/823481 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/7848

Abstract: A device includes a first transistor, a second transistor, and a dielectric structure. The first transistor is over a substrate and has a first gate structure. The second transistor is over the substrate and has a second gate structure. The dielectric structure is between the first gate structure and the second gate structure. The dielectric structure has a width increasing from a bottom position of the dielectric structure to a first position higher than the bottom position of the dielectric structure. A width of the first gate structure is less than the width of the dielectric structure at the first position.

公开(公告)号：US11532499B2

公开(公告)日：2022-12-20

申请号：US17182782

申请日：2021-02-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsai-Hao Hung ,  Ping-Cheng Ko ,  Tzu-Yang Lin ,  Fang-Yu Liu ,  Cheng-Han Wu

IPC: H01L21/687 ,  H01L21/677 ,  H01L21/67 ,  H05F1/00 ,  H01L21/66

Abstract: Semiconductor processing apparatuses and methods are provided in which an electrostatic discharge (ESD) prevention layer is utilized to prevent or reduce ESD events from occurring between a semiconductor wafer and one or more components of the apparatuses. In some embodiments, a semiconductor processing apparatus includes a wafer handling structure that is configured to support a semiconductor wafer during processing of the semiconductor wafer. The apparatus further includes an ESD prevention layer on the wafer handling structure. The ESD prevention layer includes a first material and a second material, and the second material has an electrical conductivity that is greater than an electrical conductivity of the first material.

公开(公告)号：US11011636B2

公开(公告)日：2021-05-18

申请号：US16199551

申请日：2018-11-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Han Wu ,  Yu-Ho Chiang ,  Jyh-Huei Chen ,  Jhon-Jhy Liaw

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/165 ,  H01L29/417 ,  H01L21/02 ,  H01L21/306 ,  H01L29/66

Abstract: A method for forming a FinFET device structure is provided. The method for forming a FinFET device structure includes forming a fin structure over a substrate, and forming a source/drain (S/D) structure over the fin structure. The method for forming a FinFET device structure also includes forming an inter-layer dielectric (ILD) structure covering the S/D structure, and forming a gate structure over the fin structure and adjacent to the S/D structure. The method for forming a FinFET device structure further includes forming a first hard mask layer over the gate structure, and forming a second hard mask layer over the first hard mask layer. In addition, the method for forming a FinFET device structure includes etching the ILD structure to form an opening exposing the S/D structure. The opening and a recess in the second hard mask layer are formed simultaneously.

公开(公告)号：US10527941B2

公开(公告)日：2020-01-07

申请号：US15608631

申请日：2017-05-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Yu Liu ,  Ya-Ching Chang ,  Cheng-Han Wu ,  Ching-Yu Chang ,  Chin-Hsiang Lin

IPC: G03F7/039 ,  G03F7/38 ,  G03F7/32 ,  G03F7/30

Abstract: The present disclosure provides a method for lithography patterning in accordance with some embodiments. The method includes forming a resist layer over a substrate and performing an exposing process to the resist layer. The resist layer includes a polymer backbone, an acid labile group (ALG) bonded to the polymer backbone, a sensitizer bonded to the polymer backbone, a photo-acid generator (PAG), and a thermo-base generator (TBG). The method further includes baking the resist layer at a first temperature and subsequently at a second temperature. The second temperature is higher than the first temperature. The method further includes developing the resist layer in a developer, thereby forming a patterned resist layer.

公开(公告)号：US09817315B2

公开(公告)日：2017-11-14

申请号：US14208529

申请日：2014-03-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Zhan Zhou ,  Heng-Jen Lee ,  Hsu-Yuan Liu ,  Yu-Chen Huang ,  Cheng-Han Wu ,  Shih-Che Wang ,  Ho-Yung David Hwang

IPC: G03F7/16 ,  B67D7/02 ,  B67D7/36 ,  B67D7/78

CPC classification number: G03F7/16 ,  B67D7/0294 ,  B67D7/36 ,  B67D7/78 ,  Y10T137/0318 ,  Y10T137/86187

Abstract: A photolithography system includes a variable-volume buffer tank, a dispensing system connected to the buffer tank, and a valve configured to release gas from a head space of the buffer tank while blocking the release of liquid from the head space. A storage container has an opening at the bottom and drains to the buffer tank through that opening. The buffer tank has a storage capacity sufficient to receive the full contents of the storage container. The system supplies chemical solutions to the dispensing system while keeping the chemical solutions from contact with air and other gases.

公开(公告)号：US12287575B2

公开(公告)日：2025-04-29

申请号：US18302608

申请日：2023-04-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Keng-Chu Lin ,  Joung-Wei Liou ,  Cheng-Han Wu ,  Ya Hui Chang

IPC: G03F7/038 ,  G03F7/039 ,  G03F7/11 ,  G03F7/16 ,  G03F7/20 ,  G03F7/32 ,  H01L21/027 ,  H01L21/311 ,  H01L21/3213

Abstract: A system and method for depositing a photoresist and utilizing the photoresist are provided. In an embodiment a deposition chamber is utilized along with a first precursor material comprising carbon-carbon double bonds and a second precursor material comprising repeating units to deposit the photoresist onto a substrate. The first precursor material is turned into a plasma in a remote plasma chamber prior to being introduced into the deposition chamber. The resulting photoresist comprises a carbon backbone with carbon-carbon double bonds.

公开(公告)号：US12255091B2

公开(公告)日：2025-03-18

申请号：US18516703

申请日：2023-11-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsai-Hao Hung ,  Ping-Cheng Ko ,  Tzu-Yang Lin ,  Fang-Yu Liu ,  Cheng-Han Wu

IPC: H01L21/687 ,  H01L21/66 ,  H01L21/67 ,  H01L21/677 ,  H05F1/00

Abstract: Semiconductor processing apparatuses and methods are provided in which an electrostatic discharge (ESD) prevention layer is utilized to prevent or reduce ESD events from occurring between a semiconductor wafer and one or more components of the apparatuses. In some embodiments, a semiconductor processing apparatus includes a wafer handling structure that is configured to support a semiconductor wafer during processing of the semiconductor wafer. The apparatus further includes an ESD prevention layer on the wafer handling structure. The ESD prevention layer includes a first material and a second material, and the second material has an electrical conductivity that is greater than an electrical conductivity of the first material.