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公开(公告)号：US11424359B2
公开(公告)日：2022-08-23
申请号：US17142618
申请日：2021-01-06
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Hung-Chou Lin , Yi-Cheng Chiu , Karthick Murukesan , Yi-Min Chen , Shiuan-Jeng Lin , Wen-Chih Chiang , Chen-Chien Chang , Chih-Yuan Chan , Kuo-Ming Wu , Chun-Lin Tsai
IPC: H01L29/78 , H01L29/08 , H01L29/40 , H01L29/06 , H01L29/423
Abstract: A high-voltage semiconductor device structure is provided. The high-voltage semiconductor device structure includes a semiconductor substrate, a source ring in the semiconductor substrate, and a drain region in the semiconductor substrate. The high-voltage semiconductor device structure also includes a doped ring surrounding sides and a bottom of the source ring and a well region surrounding sides and bottoms of the drain region and the doped ring. The well region has a conductivity type opposite to that of the doped ring. The high-voltage semiconductor device structure further includes a conductor electrically connected to the drain region and extending over and across a periphery of the well region. In addition, the high-voltage semiconductor device structure includes a shielding element ring between the conductor and the semiconductor substrate. The shielding element ring extends over and across the periphery of the well region.
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公开(公告)号：US11407636B2
公开(公告)日：2022-08-09
申请号：US16122180
申请日：2018-09-05
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Shyh-Wei Cheng , Chih-Yu Wang , Hsi-Cheng Hsu , Ji-Hong Chiang , Jui-Chun Weng , Shiuan-Jeng Lin , Wei-Ding Wu , Ching-Hsiang Hu
Abstract: The present disclosure, in some embodiments, relates to a method of forming a micro-electromechanical system (MEMS) package. The method includes forming one or more depressions within a capping substrate. A back-side of a MEMS substrate is bonded to the capping substrate after forming the one or more depressions, so that the one or more depressions define one or more cavities between the capping substrate and the MEMS substrate. A front-side of the MEMS substrate is selectively etched to form one or more trenches extending through the MEMS substrate, and one or more polysilicon vias are formed within the one or more trenches. A conductive bonding structure is formed on the front-side of the MEMS substrate at a location contacting the one or more polysilicon vias. The MEMS substrate is bonded to a CMOS substrate having one or more semiconductor devices by way of the conductive bonding structure.
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公开(公告)号：US10964781B2
公开(公告)日：2021-03-30
申请号：US16199483
申请日：2018-11-26
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Yi-Cheng Chiu , Wen-Chih Chiang , Chun Lin Tsai , Kuo-Ming Wu , Shiuan-Jeng Lin , Yi-Min Chen , Hung-Chou Lin , Karthick Murukesan
IPC: H01L29/06 , H01L29/10 , H01L23/528 , H01L23/522 , H01L29/78 , H01L29/66 , H01L29/8605
Abstract: The present disclosure, in some embodiments, relates to a high voltage resistor device. The device includes a buried well region disposed within a substrate and having a first doping type. A drift region is disposed within the substrate and contacts the buried well region. The drift region has the first doping type. A body region is disposed within the substrate and has a second doping type. The body region laterally contacts the drift region and vertically contacts the buried well region. An isolation structure is over the drift region and a resistor structure is over the isolation structure.
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公开(公告)号：US20170107097A1
公开(公告)日：2017-04-20
申请号：US14980297
申请日：2015-12-28
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Shyh-Wei Cheng , Chih-Yu Wang , Hsi-Cheng Hsu , Ji-Hong Chiang , Jui-Chun Weng , Shiuan-Jeng Lin , Wei-Ding Wu , Ching-Hsiang Hu
CPC classification number: B81B7/007 , B81B7/0006 , B81B2207/012 , B81B2207/096 , B81C1/00238 , B81C1/00301 , B81C2201/013 , B81C2203/0109 , B81C2203/0118 , B81C2203/037 , B81C2203/0792
Abstract: The present disclosure relates to micro-electromechanical system (MEMS) package that uses polysilicon inter-tier connections to provide for a low parasitic capacitance in MEM device signals, and a method of formation. In some embodiments, the MEMS package has a CMOS substrate with one or more semiconductor devices arranged within a semiconductor body. A MEMS substrate having an ambulatory element is connected to the CMOS substrate by a conductive bonding structure. The conductive bonding structure is arranged on a front-side of the MEMS substrate at a location laterally offset from the ambulatory element. One or more polysilicon vias extend through the conductive MEMS substrate to the bonding structure. The one or more polysilicon vias are configured to electrically couple the MEMS substrate to the CMOS substrate. By connecting the MEMS substrate to the CMOS substrate using the polysilicon vias, the parasitic capacitance and form factor of the MEMS package are reduced.
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公开(公告)号：US20200373380A1
公开(公告)日：2020-11-26
申请号：US16991385
申请日：2020-08-12
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Guo-Jyun Luo , Chen-Chien Chang , Chiu-Hua Chung , Shiuan-Jeng Lin , Han-Zong Pan
IPC: H01L49/02 , H01L27/08 , H01L27/06 , H01L21/285
Abstract: The present disclosure relates to a semiconductor device structure. The semiconductor device structure has a first conductive layer disposed over a substrate and a first capacitor dielectric layer comprising a first dielectric material disposed over the first conductive layer. A second conductive layer is over the first capacitor dielectric layer, a second capacitor dielectric layer comprising a second dielectric material is disposed over the second conductive layer, and a third conductive layer is over the second capacitor dielectric layer. A first barrier layer is disposed between an upper surface of the first conductive layer and a lower surface of the first capacitor dielectric layer.
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Patent Agency Ranking
公开(公告)号：US10679987B2
公开(公告)日：2020-06-09
申请号：US16128578
申请日：2018-09-12
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Karthick Murukesan , Wen-Chih Chiang , Chiu-Hua Chung , Chun Lin Tsai , Kuo-Ming Wu , Shiuan-Jeng Lin , Tien Sheng Lin , Yi-Min Chen , Hung-Chou Lin , Yi-Cheng Chiu
IPC: H01L29/06 , H01L27/07 , H01L21/8234 , H01L21/761 , H01L29/78 , H01L27/06 , H01L29/861
Abstract: Various embodiments of the present application are directed towards an integrated circuit (IC) in which a bootstrap metal-oxide-semiconductor (MOS) device is integrated with a high voltage metal-oxide-semiconductor (HVMOS) device and a high voltage junction termination (HVJT) device. In some embodiments, a drift well is in the semiconductor substrate. The drift well has a first doping type and has a ring-shaped top layout. A first switching device is on the drift well. A second switching device is on the semiconductor substrate, at an indent in a sidewall the drift well. A peripheral well is in the semiconductor substrate and has a second doping type opposite the first doping type. The peripheral well surrounds the drift well, the first switching device, and the second switching device, and further separates the second switching device from the drift well and the first switching device.
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公开(公告)号：US10297661B2
公开(公告)日：2019-05-21
申请号：US15694341
申请日：2017-09-01
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Yi-Cheng Chiu , Wen-Chih Chiang , Chun Lin Tsai , Kuo-Ming Wu , Shiuan-Jeng Lin , Yi-Min Chen , Hung-Chou Lin , Karthick Murukesan
IPC: H01L29/06 , H01L23/522 , H01L23/528 , H01L29/78 , H01L29/10 , H01L29/66
Abstract: The present disclosure relates to a high voltage resistor device that is able to receive high voltages using a small footprint, and an associated method of fabrication. In some embodiments, the high voltage resistor device has a substrate including a first region with a first doping type, and a drift region arranged within the substrate over the first region and having a second doping type. A body region having the first doping type laterally contacts the drift region. A drain region having the second doping type is arranged within the drift region, and an isolation structure is over the substrate between the drain region and the body region. A resistor structure is over the isolation structure and has a high-voltage terminal coupled to the drain region and a low-voltage terminal coupled to a gate structure over the isolation structure.
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公开(公告)号：US20190131296A1
公开(公告)日：2019-05-02
申请号：US16128578
申请日：2018-09-12
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Karthick Murukesan , Wen-Chih Chiang , Chiu-Hua Chung , Chun Lin Tsai , Kuo-Ming Wu , Shiuan-Jeng Lin , Tien Sheng Lin , Yi-Min Chen , Hung-Chou Lin , Yi-Cheng Chiu
IPC: H01L27/07 , H01L21/8234
Abstract: Various embodiments of the present application are directed towards an integrated circuit (IC) in which a bootstrap metal-oxide-semiconductor (MOS) device is integrated with a high voltage metal-oxide-semiconductor (HVMOS) device and a high voltage junction termination (HVJT) device. In some embodiments, a drift well is in the semiconductor substrate. The drift well has a first doping type and has a ring-shaped top layout. A first switching device is on the drift well. A second switching device is on the semiconductor substrate, at an indent in a sidewall the drift well. A peripheral well is in the semiconductor substrate and has a second doping type opposite the first doping type. The peripheral well surrounds the drift well, the first switching device, and the second switching device, and further separates the second switching device from the drift well and the first switching device.
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公开(公告)号：US20180370790A1
公开(公告)日：2018-12-27
申请号：US16122180
申请日：2018-09-05
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Shyh-Wei Cheng , Chih-Yu Wang , Hsi-Cheng Hsu , Ji-Hong Chiang , Jui-Chun Weng , Shiuan-Jeng Lin , Wei-Ding Wu , Ching-Hsiang Hu
Abstract: The present disclosure, in some embodiments, relates to a method of forming a micro-electromechanical system (MEMS) package. The method includes forming one or more depressions within a capping substrate. A back-side of a MEMS substrate is bonded to the capping substrate after forming the one or more depressions, so that the one or more depressions define one or more cavities between the capping substrate and the MEMS substrate. A front-side of the MEMS substrate is selectively etched to form one or more trenches extending through the MEMS substrate, and one or more polysilicon vias are formed within the one or more trenches. A conductive bonding structure is formed on the front-side of the MEMS substrate at a location contacting the one or more polysilicon vias. The MEMS substrate is bonded to a CMOS substrate having one or more semiconductor devices by way of the conductive bonding structure.
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公开(公告)号：US10155656B2
公开(公告)日：2018-12-18
申请号：US14980297
申请日：2015-12-28
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Shyh-Wei Cheng , Chih-Yu Wang , Hsi-Cheng Hsu , Ji-Hong Chiang , Jui-Chun Weng , Shiuan-Jeng Lin , Wei-Ding Wu , Ching-Hsiang Hu
Abstract: The present disclosure relates to micro-electromechanical system (MEMS) package that uses polysilicon inter-tier connections to provide for a low parasitic capacitance in MEM device signals, and a method of formation. In some embodiments, the MEMS package has a CMOS substrate with one or more semiconductor devices arranged within a semiconductor body. A MEMS substrate having an ambulatory element is connected to the CMOS substrate by a conductive bonding structure. The conductive bonding structure is arranged on a front-side of the MEMS substrate at a location laterally offset from the ambulatory element. One or more polysilicon vias extend through the conductive MEMS substrate to the bonding structure. The one or more polysilicon vias are configured to electrically couple the MEMS substrate to the CMOS substrate. By connecting the MEMS substrate to the CMOS substrate using the polysilicon vias, the parasitic capacitance and form factor of the MEMS package are reduced.
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