公开(公告)号：US11595064B2

公开(公告)日：2023-02-28

申请号：US17401398

申请日：2021-08-13

Applicant: Texas Instruments Incorporated

Inventor： Raghu Ganesan ,  Saravanakkumar Radhakrishnan ,  Gaurav Aggarwal ,  Rallabandi V Lakshmi Annapurna

IPC: H04B1/04 ,  H04L25/03 ,  H04L25/02 ,  H04B1/30

Abstract: A receiver circuit includes an analog-to-digital converter (ADC), a decision feedback equalizer (DFE), a slicer, and a timing error detector (TED). The DFE is coupled to the ADC, and includes a first tap and a second tap. The slicer is coupled to the DFE. The TED is coupled to the slicer. The TED is configured to initialize timing of a sampling clock provided to the ADC while initializing the second tap of the DFE and holding the first tap of the DFE at a constant value.