公开(公告)号：US12028192B2

公开(公告)日：2024-07-02

申请号：US18111862

申请日：2023-02-20

Applicant: Texas Instruments Incorporated

Inventor： Raghu Ganesan ,  Saravanakkumar Radhakrishnan ,  Gaurav Aggarwal

IPC: H04L25/03 ,  H04L7/00 ,  H04L7/033

CPC classification number: H04L25/03057 ,  H04L7/0079 ,  H04L7/033

Abstract: An example apparatus includes: a feed forward equalizer (FFE) with a FFE output, adder circuitry with a first adder input, a second adder input, and a first adder output, the first adder input coupled to the FFE output, a multiplexer (MUX) with a first MUX input, a second MUX input, and a MUX output, the first MUX input coupled to the first adder output, the second MUX input coupled to the FFE output, a decision feedback equalizer (DFE) with a DFE output coupled to the second adder input, and a timing error detector (TED) with a first TED input coupled to the MUX output.

公开(公告)号：US20220070031A1

公开(公告)日：2022-03-03

申请号：US17461575

申请日：2021-08-30

Applicant: Texas Instruments Incorporated

Inventor： Raghu Ganesan ,  Saravanakkumar Radhakrishnan ,  Gaurav Aggarwal

IPC: H04L25/03 ,  H04L7/033 ,  H04L7/00

Abstract: An example apparatus includes: a feed forward equalizer (FFE) with a FFE output, adder circuitry with a first adder input, a second adder input, and a first adder output, the first adder input coupled to the FFE output, a multiplexer (MUX) with a first MUX input, a second MUX input, and a MUX output, the first MUX input coupled to the first adder output, the second MUX input coupled to the FFE output, a decision feedback equalizer (DFE) with a DFE output coupled to the second adder input, and a timing error detector (TED) with a first TED input coupled to the MUX output.

公开(公告)号：US20230208675A1

公开(公告)日：2023-06-29

申请号：US18117511

申请日：2023-03-06

Applicant: Texas Instruments Incorporated

Inventor： Raghu Ganesan ,  Saravanakkumar Radhakrishnan ,  Gaurav Aggarwal

IPC: H04L12/40 ,  H04L12/64 ,  H04L25/03 ,  H04L43/0823

CPC classification number: H04L12/40039 ,  H04L12/6418 ,  H04L25/03267 ,  H04L43/0823 ,  H04L2012/6467 ,  H04L2027/0069

Abstract: A receiver circuit includes a feedback loop including a device. The receiver circuit also includes a register and a sequencer. The sequencer is configured to, responsive to an error signal being below a threshold value, cause the register to store a value indicative of the state of the feedback loop. The sequencer is also configured to cause the feedback loop to transition to a lower power state, and, responsive to a detected wake-up event, cause the previously stored value indicative of the state of the feedback loop to be loaded from the register into the device and enable the feedback loop.

公开(公告)号：US11601302B2

公开(公告)日：2023-03-07

申请号：US17082208

申请日：2020-10-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Raghu Ganesan ,  Saravanakkumar Radhakrishnan ,  Gaurav Aggarwal

IPC: H04L25/03 ,  H04L27/00 ,  H04L12/40 ,  H04L12/64 ,  H04L43/0823

Abstract: A receiver circuit includes a feedback loop including a device. The receiver circuit also includes a register and a sequencer. The sequencer is configured to, responsive to an error signal being below a threshold value, cause the register to store a value indicative of the state of the feedback loop. The sequencer is also configured to cause the feedback loop to transition to a lower power state, and, responsive to a detected wake-up event, cause the previously stored value indicative of the state of the feedback loop to be loaded from the register into the device and enable the feedback loop.

公开(公告)号：US11469785B2

公开(公告)日：2022-10-11

申请号：US17200060

申请日：2021-03-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Raghu Ganesan ,  Gaurav Aggarwal ,  Rahul Koppisetti ,  Rallabandi V Lakshmi Annapurna ,  Saravanakkumar Radhakrishnan ,  Kalpesh Laxmanbhai Rajai

IPC: H04B1/10 ,  H04B1/12 ,  H04B1/16 ,  H03M1/00 ,  H03M1/06 ,  H03M1/50

Abstract: A receiver circuit includes an ADC, a processing channel, and an interference detection path. The processing channel is configured to process data samples provided by the ADC, and includes a notch filter. The interference detection path is configured to detect interference in the data samples, and includes a slicer, a slicer error circuit, and an interference detection circuit. The slicer is configured to slice input of the notch filter. The slicer error circuit is configured to compute an error of the slicer. The interference detection circuit configured to detect an interference signal in the error of the slicer, and set the notch filter to attenuate the interference signal.

公开(公告)号：US11588667B2

公开(公告)日：2023-02-21

申请号：US17461575

申请日：2021-08-30

Applicant: Texas Instruments Incorporated

Inventor： Raghu Ganesan ,  Saravanakkumar Radhakrishnan ,  Gaurav Aggarwal

IPC: H04L25/03 ,  H04L7/00 ,  H04L7/033

Abstract: An example apparatus includes: a feed forward equalizer (FFE) with a FFE output, adder circuitry with a first adder input, a second adder input, and a first adder output, the first adder input coupled to the FFE output, a multiplexer (MUX) with a first MUX input, a second MUX input, and a MUX output, the first MUX input coupled to the first adder output, the second MUX input coupled to the FFE output, a decision feedback equalizer (DFE) with a DFE output coupled to the second adder input, and a timing error detector (TED) with a first TED input coupled to the MUX output.

公开(公告)号：US12267182B2

公开(公告)日：2025-04-01

申请号：US18117511

申请日：2023-03-06

Applicant: Texas Instruments Incorporated

Inventor： Raghu Ganesan ,  Saravanakkumar Radhakrishnan ,  Gaurav Aggarwal

IPC: H04L12/40 ,  H04L25/03

Abstract: A receiver circuit includes a feedback loop including a device. The receiver circuit also includes a register and a sequencer. The sequencer is configured to, responsive to an error signal being below a threshold value, cause the register to store a value indicative of the state of the feedback loop. The sequencer is also configured to cause the feedback loop to transition to a lower power state, and, responsive to a detected wake-up event, cause the previously stored value indicative of the state of the feedback loop to be loaded from the register into the device and enable the feedback loop.

公开(公告)号：US20230208685A1

公开(公告)日：2023-06-29

申请号：US18111862

申请日：2023-02-20

Applicant: Texas Instruments Incorporated

Inventor： Raghu Ganesan ,  Saravanakkumar Radhakrishnan ,  Gaurav Aggarwal

IPC: H04L25/03 ,  H04L7/00 ,  H04L7/033

CPC classification number: H04L25/03057 ,  H04L7/0079 ,  H04L7/033

Abstract: An example apparatus includes: a feed forward equalizer (FFE) with a FFE output, adder circuitry with a first adder input, a second adder input, and a first adder output, the first adder input coupled to the FFE output, a multiplexer (MUX) with a first MUX input, a second MUX input, and a MUX output, the first MUX input coupled to the first adder output, the second MUX input coupled to the FFE output, a decision feedback equalizer (DFE) with a DFE output coupled to the second adder input, and a timing error detector (TED) with a first TED input coupled to the MUX output.

公开(公告)号：US11316707B2

公开(公告)日：2022-04-26

申请号：US17199142

申请日：2021-03-11

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Kalpesh Laxmanbhai Rajai ,  Saravanakkumar Radhakrishnan ,  Gaurav Aggarwal ,  Raghu Ganesan ,  Rallabandi V Lakshmi Annapurna

IPC: H04L25/03 ,  H04L12/12 ,  H03H17/06

Abstract: A method includes receiving an input signal at a filter, where the filter includes a plurality of filter taps, and where each of a first filter tap and a second filter tap has a weighting coefficient. The method also includes shutting down the first filter tap based on the weighting coefficient of the first filter tap being below a threshold and the weighting coefficient of the second filter tap being below the threshold, where the second filter tap is next to the first filter tap.

公开(公告)号：US20210288836A1

公开(公告)日：2021-09-16

申请号：US17082208

申请日：2020-10-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Raghu GANESAN ,  Saravanakkumar Radhakrishana ,  Gaurav Aggarwal

IPC: H04L12/40 ,  H04L12/64 ,  H04L12/26 ,  H04L25/03

Abstract: A receiver circuit includes a feedback loop including a device. The receiver circuit also includes a register and a sequencer. The sequencer is configured to, responsive to an error signal being below a threshold value, cause the register to store a value indicative of the state of the feedback loop. The sequencer is also configured to cause the feedback loop to transition to a lower power state, and, responsive to a detected wake-up event, cause the previously stored value indicative of the state of the feedback loop to be loaded from the register into the device and enable the feedback loop.