公开(公告)号：US09817931B1

公开(公告)日：2017-11-14

申请号：US14562382

申请日：2014-12-05

Applicant: The Mathworks, Inc.

Inventor： Yongfeng Gu ,  Girish Venkataramani ,  Rama Kokku

IPC: G06F17/50

CPC classification number: G06F17/505 ,  G06F17/5022

Abstract: Systems and methods automatically generate optimized hardware description language (HDL) code for an executable model. An intermediate representation is generated for the executable model, which includes model elements. The intermediate representation includes nodes corresponding to the model elements. The HDL code is generated from the intermediate representation. A synthesis tool chain performs hardware synthesis using the HDL code. The synthesis tool chain generates performance characteristics of hardware components defined by the synthesis tool chain. The performance characteristics are mapped to the nodes of the intermediate representation, and one or more performance bottlenecks are identified. At least one optimization technique is applied to the intermediate representation to produce a revised intermediate representation, which is then used to generate new HDL code. The process may be repeated until the performance bottlenecks are eliminated or a termination criterion is met.

公开(公告)号：US09779195B2

公开(公告)日：2017-10-03

申请号：US14640239

申请日：2015-03-06

Applicant: The MathWorks, Inc.

Inventor： Yongfeng Gu ,  Girish Venkataramani

IPC: G06F17/50

CPC classification number: G06F17/505 ,  G06F17/5022 ,  G06F17/504 ,  G06F17/5081

Abstract: A system and method tests for functional equivalence prior to automatically retiming a high-level specification. An Intermediate Representation (IR) includes one or more graphs or trees based on the high-level specification. A functional equivalence (FE) analyzer determines whether one or more components in the graph meet certain value and state conditions and thus is a candidate for retiming. A scheduler can use components that fail FE as a retiming boundary.