公开(公告)号：US10078717B1

公开(公告)日：2018-09-18

申请号：US14562647

申请日：2014-12-05

Applicant: The MathWorks, Inc.

Inventor： Girish Venkataramani ,  Yongfeng Gu ,  Rama Kokku

IPC: G06F17/50

CPC classification number: G06F17/505 ,  G06F17/5031 ,  G06F17/5081 ,  G06F2217/80 ,  G06F2217/82 ,  G06F2217/84

Abstract: Systems and methods automatically generate optimized hardware description language code for a model created in a modeling environment. A training tool selects and provides scripts to a hardware synthesis tool chain that direct the tool chain to synthesize hardware components for core components of the modeling environment. A report generated by the tool chain is evaluated to extract performance data for the core components, and the performance data is stored in a library. An optimization tool estimates the performance of the model using the performance data in the library. Based on the performance estimate and an analysis of the model, the optimization tool selects an optimization technique which it applies to the model generating a revised. Estimating performance, and selecting and applying optimizations may be repeated until a performance constraint is satisfied or a termination criterion is met.

公开(公告)号：US09817931B1

公开(公告)日：2017-11-14

申请号：US14562382

申请日：2014-12-05

Applicant: The Mathworks, Inc.

Inventor： Yongfeng Gu ,  Girish Venkataramani ,  Rama Kokku

IPC: G06F17/50

CPC classification number: G06F17/505 ,  G06F17/5022

Abstract: Systems and methods automatically generate optimized hardware description language (HDL) code for an executable model. An intermediate representation is generated for the executable model, which includes model elements. The intermediate representation includes nodes corresponding to the model elements. The HDL code is generated from the intermediate representation. A synthesis tool chain performs hardware synthesis using the HDL code. The synthesis tool chain generates performance characteristics of hardware components defined by the synthesis tool chain. The performance characteristics are mapped to the nodes of the intermediate representation, and one or more performance bottlenecks are identified. At least one optimization technique is applied to the intermediate representation to produce a revised intermediate representation, which is then used to generate new HDL code. The process may be repeated until the performance bottlenecks are eliminated or a termination criterion is met.

公开(公告)号：US10423733B1

公开(公告)日：2019-09-24

申请号：US15099111

申请日：2016-04-14

Applicant: The Mathworks, Inc.

Inventor： Girish Venkataramani ,  Yongfeng Gu ,  Rama Kokku ,  Sanmukh Rao Kuppannagari

IPC: G06F17/50 ,  G06F8/30

Abstract: A system and method generates optimized code for a source model. The system may include a resource sharing optimizer that evaluates the source model and replaces multiple model elements of the source model that are functionally equivalent with a single shared model element. The model elements replaced with the single shared model element may have different fixed point data types. The resource sharing optimizer may convert some of the fixed point data types to a common fixed point data type.

公开(公告)号：US10114917B1

公开(公告)日：2018-10-30

申请号：US15225193

申请日：2016-08-01

Applicant: The MathWorks, Inc.

Inventor： Girish Venkataramani ,  Purshottam Vishwakarma ,  Rama Kokku

IPC: G06F17/50

Abstract: Systems and methods automatically generate code from an executable model. The code may be generated from one or more in-memory representations constructed for the model. The in-memory representations may be analyzed, and portions that can be mapped to DSP slices of a programmable logic device may be identified. The portions may be modified based on information for a particular programmable logic device, such as the structure of the device's DSP slices. The modifications may ensure that elements of the generated code get mapped to DSP slices, when the generated code is used to synthesize the programmable logic device.