公开(公告)号：US09972498B2

公开(公告)日：2018-05-15

申请号：US15081932

申请日：2016-03-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Fu-Shou Tsai ,  Yu-Ting Li ,  Chih-Hsun Lin ,  Li-Chieh Hsu ,  Yi-Liang Liu ,  Po-Cheng Huang ,  Kun-Ju Li ,  Wen-Chin Lin

IPC: B23P15/00 ,  C03C25/00 ,  C23F1/00 ,  B44C1/22 ,  C03C15/00 ,  C03C25/68 ,  H01L21/28 ,  H01L29/66 ,  H01L21/02 ,  H01L21/3105

CPC classification number: H01L21/28247 ,  H01L21/0223 ,  H01L21/02247 ,  H01L21/28088 ,  H01L21/28114 ,  H01L21/31053 ,  H01L21/31056 ,  H01L29/66545

Abstract: A method of fabricating a gate cap layer includes providing a substrate with an interlayer dielectric disposed thereon, wherein a recess is disposed in the interlayer dielectric and a metal gate fills in a lower portion of the recess. Later, a cap material layer is formed to cover the interlayer dielectric and fill in an upper portion of the recess. After that, a first sacrifice layer and a second sacrifice layer are formed in sequence to cover the cap material layer. The first sacrifice layer has a composition different from a composition of the cap material layer. The second sacrifice layer has a composition the same as the composition of the cap material layer. Next, a chemical mechanical polishing process is preformed to remove the second sacrifice layer, the first sacrifice layer and the cap material layer above a top surface of the interlayer dielectric.

公开(公告)号：US09887158B1

公开(公告)日：2018-02-06

申请号：US15340982

申请日：2016-11-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kun-Ju Li ,  Kuo-Chin Hung ,  Min-Chuan Tsai ,  Wei-Chuan Tsai ,  Yi-Han Liao ,  Chun-Tsen Lu ,  Fu-Shou Tsai ,  Li-Chieh Hsu

IPC: H01L23/52 ,  H01L29/41 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L29/417 ,  H01L21/768

CPC classification number: H01L23/5283 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76883 ,  H01L23/485 ,  H01L23/5228 ,  H01L23/53238 ,  H01L23/53266 ,  H01L29/41758 ,  H01L29/66628 ,  H01L29/7833

Abstract: A conductive structure includes a substrate including a first dielectric layer formed thereon, a first trench formed in the first dielectric layer, a first barrier layer formed in the first trench, a first nucleation layer formed on the first barrier layer, a first metal layer formed on the first nucleation layer, and a first high resistive layer sandwiched in between the first barrier layer and the first metal layer.

公开(公告)号：US20180012771A1

公开(公告)日：2018-01-11

申请号：US15678117

申请日：2017-08-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Li-Chieh Hsu ,  Fu-Shou Tsai ,  Yu-Ting Li ,  Yi-Liang Liu ,  Kun-Ju Li

IPC: H01L21/3105 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L21/31053 ,  H01L21/31055 ,  H01L29/0653 ,  H01L29/7851

Abstract: A method of planarizing a substrate surface is disclosed. A substrate having a major surface of a material layer is provided. The major surface of the material layer comprises a first region with relatively low removal rate and a second region of relatively high removal rate. A photoresist pattern is formed on the material layer. The photoresist pattern masks the second region, while exposes at least a portion of the first region. At least a portion of the material layer not covered by the photoresist pattern is etched away. A polish stop layer is deposited on the material layer. A cap layer is deposited on the polish stop layer. A chemical mechanical polishing (CMP) process is performed to polish the cap layer.

公开(公告)号：US09773682B1

公开(公告)日：2017-09-26

申请号：US15201628

申请日：2016-07-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Li-Chieh Hsu ,  Fu-Shou Tsai ,  Yu-Ting Li ,  Yi-Liang Liu ,  Kun-Ju Li

IPC: H01L21/3105 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L21/31053 ,  H01L21/31055 ,  H01L29/0653 ,  H01L29/7851

Abstract: A method of planarizing a substrate surface is disclosed. A substrate having a major surface of a material layer is provided. The major surface of the material layer comprises a first region with relatively low removal rate and a second region of relatively high removal rate. A photoresist pattern is formed on the material layer. The photoresist pattern masks the second region, while exposes at least a portion of the first region. At least a portion of the material layer not covered by the photoresist pattern is etched away. A polish stop layer is deposited on the material layer. A cap layer is deposited on the polish stop layer. A chemical mechanical polishing (CMP) process is performed to polish the cap layer.

公开(公告)号：US09748147B1

公开(公告)日：2017-08-29

申请号：US15214467

申请日：2016-07-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Fan Li ,  Li-Wei Feng ,  Li-Chieh Hsu ,  Chun-Jen Chen ,  I-Cheng Hu ,  Tien-I Wu ,  Yu-Shu Lin ,  Neng-Hui Yang

IPC: H01L21/20 ,  H01L21/8238 ,  H01L21/265 ,  H01L21/02 ,  H01L21/308

CPC classification number: H01L21/823821 ,  H01L21/0243 ,  H01L21/0245 ,  H01L21/02521 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02587 ,  H01L21/0262 ,  H01L21/02634 ,  H01L21/02636 ,  H01L21/02639 ,  H01L21/02661 ,  H01L21/2652 ,  H01L21/3086 ,  H01L21/823807 ,  H01L21/8258

Abstract: A method of fabricating an epitaxial layer includes providing a silicon substrate. A dielectric layer covers the silicon substrate. A recess is formed in the silicon substrate and the dielectric layer. A selective epitaxial growth process and a non-selective epitaxial growth process are performed in sequence to respectively form a first epitaxial layer and a second epitaxial layer. The first epitaxial layer does not cover the top surface of the dielectric layer. The recess is filled by the first epitaxial layer and the second epitaxial layer. Finally, the first epitaxial layer and the second epitaxial layer are planarized.

公开(公告)号：US20170162396A1

公开(公告)日：2017-06-08

申请号：US15081932

申请日：2016-03-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Fu-Shou Tsai ,  Yu-Ting Li ,  Chih-Hsun Lin ,  Li-Chieh Hsu ,  Yi-Liang Liu ,  Po-Cheng Huang ,  Kun-Ju Li ,  Wen-Chin Lin

IPC: H01L21/28 ,  H01L21/02 ,  H01L21/3105 ,  H01L29/66

CPC classification number: H01L21/28247 ,  H01L21/0223 ,  H01L21/02247 ,  H01L21/28088 ,  H01L21/28114 ,  H01L21/31053 ,  H01L21/31056 ,  H01L29/66545

Abstract: A method of fabricating a gate cap layer includes providing a substrate with an interlayer dielectric disposed thereon, wherein a recess is disposed in the interlayer dielectric and a metal gate fills in a lower portion of the recess. Later, a cap material layer is formed to cover the interlayer dielectric and fill in an upper portion of the recess. After that, a first sacrifice layer and a second sacrifice layer are formed in sequence to cover the cap material layer. The first sacrifice layer has a composition different from a composition of the cap material layer. The second sacrifice layer has a composition the same as the composition of the cap material layer. Next, a chemical mechanical polishing process is preformed to remove the second sacrifice layer, the first sacrifice layer and the cap material layer above a top surface of the interlayer dielectric.

公开(公告)号：US20150333000A1

公开(公告)日：2015-11-19

申请号：US14279602

申请日：2014-05-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsin-Kuo Hsu ,  Li-Chieh Hsu ,  Hsiang-Hao Chen ,  Chung-Wei Hsueh

IPC: H01L23/528 ,  H01L21/321 ,  H01L21/3213 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/528 ,  H01L21/3212 ,  H01L21/32134 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for manufacturing a semiconductor device and a device manufactured using the same are provided. According to the embodiment, substrate with a dielectric layer formed thereon is provided. Plural trenches are defined in the dielectric layer, and the trenches are isolated by the dielectric layer. A first barrier layer is formed in the trenches as barrier liners of the trenches, followed by filling the trenches with a conductor. Then, the conductor in the trenches is partially removed to form a plurality of recesses, wherein remained conductor has a flat surface. Next, a second barrier layer is formed in the recesses as barrier caps of the trenches.

Abstract translation: 提供一种制造半导体器件的方法和使用其制造的器件。 根据本实施例，提供了形成有电介质层的基板。 在电介质层中限定多个沟槽，并且通过电介质层隔离沟槽。 在沟槽中形成第一阻挡层作为沟槽的阻挡层，然后用导体填充沟槽。 然后，沟槽中的导体被部分地去除以形成多个凹槽，其中保留的导体具有平坦的表面。 接下来，在凹槽中形成第二阻挡层作为沟槽的阻挡盖。

公开(公告)号：US10722998B2

公开(公告)日：2020-07-28

申请号：US15719515

申请日：2017-09-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Li-Chieh Hsu ,  Fu-Shou Tsai ,  Kun-Ju Li ,  Po-Cheng Huang ,  Chun-Liang Liu

IPC: B24B37/24 ,  B24B37/22 ,  B24B37/26

Abstract: The present invention provides a wafer polishing pad, the wafer polishing pad includes a polishing material layer, a plurality of recesses are formed on the top surface of the polishing material layer, and a warning element disposed within the polishing material layer, the warning element and the polishing material layer have different colors. The feature of the invention is that forming a warning element in the polishing material layer, when the visible state of the warning element is changed, for example, when the warning element appears, disappears or changes the shapes, it means that the wafer polishing pad needs to be replaced. In this way, the user can confirm the destroying situation of the wafer polishing pad easily, and also improving the manufacturing process efficiency.

公开(公告)号：US20190070706A1

公开(公告)日：2019-03-07

申请号：US15719515

申请日：2017-09-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Li-Chieh Hsu ,  Fu-Shou Tsai ,  Kun-Ju Li ,  Po-Cheng Huang ,  Chun-Liang Liu

IPC: B24B37/22 ,  B24B37/26

CPC classification number: B24B37/22 ,  B24B37/24 ,  B24B37/26 ,  B24D2205/00

Abstract: The present invention provides a wafer polishing pad, the wafer polishing pad includes a polishing material layer, a plurality of recesses are formed on the top surface of the polishing material layer, and a warning element disposed within the polishing material layer, the warning element and the polishing material layer have different colors. The feature of the invention is that forming a warning element in the polishing material layer, when the visible state of the warning element is changed, for example, when the warning element appears, disappears or changes the shapes, it means that the wafer polishing pad needs to be replaced. In this way, the user can confirm the destroying situation of the wafer polishing pad easily, and also improving the manufacturing process efficiency.

公开(公告)号：US10049887B2

公开(公告)日：2018-08-14

申请号：US15678117

申请日：2017-08-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Li-Chieh Hsu ,  Fu-Shou Tsai ,  Yu-Ting Li ,  Yi-Liang Liu ,  Kun-Ju Li

IPC: H01L21/3105 ,  H01L29/06 ,  H01L29/78

Abstract: A method of planarizing a substrate surface is disclosed. A substrate having a major surface of a material layer is provided. The major surface of the material layer comprises a first region with relatively low removal rate and a second region of relatively high removal rate. A photoresist pattern is formed on the material layer. The photoresist pattern masks the second region, while exposes at least a portion of the first region. At least a portion of the material layer not covered by the photoresist pattern is etched away. A polish stop layer is deposited on the material layer. A cap layer is deposited on the polish stop layer. A chemical mechanical polishing (CMP) process is performed to polish the cap layer.