公开(公告)号：US20210273076A1

公开(公告)日：2021-09-02

申请号：US16802564

申请日：2020-02-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yang-Ju Lu ,  Chun-Yi Wang ,  Fu-Shou Tsai ,  Yong-Yi Lin ,  Ching-Yang Chuang ,  Wen-Chin Lin ,  Hsin-Kuo Hsu

IPC: H01L29/66 ,  H01L21/3105 ,  H01L21/02

Abstract: A method of forming a gate includes the following steps. A gate structure is formed on a substrate. An etch stop layer is formed on the gate structure and the substrate. A dielectric layer is formed to cover the etch stop layer. The dielectric layer is planarized to form a planarized top surface of the dielectric layer and expose a portion of the etch stop layer on the gate structure. An oxygen containing treatment is performed to form an oxygen containing layer on the exposed etch stop layer. A deposition process is performed to form an oxide layer covering the planarized top surface of the dielectric layer and the oxygen containing layer.

公开(公告)号：US10923481B2

公开(公告)日：2021-02-16

申请号：US16151323

申请日：2018-10-03

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Yu-Ting Li ,  Jen-Chieh Lin ,  Wen-Chin Lin ,  Po-Cheng Huang ,  Fu-Shou Tsai

IPC: H01L27/10 ,  H01L27/108 ,  H01L27/06 ,  H01L21/8234

Abstract: A semiconductor IC structure includes a substrate including at least a memory cell region and a peripheral region defined thereon, a plurality of memory cells formed in the memory cell region, at least an active device formed in the peripheral region, a plurality of contact plugs formed in the memory cell region, and at least a bit line formed in the memory cell region. The contact plugs are physically and electrically connected to the bit line. More important, bottom surfaces of the contact plugs are lower a surface of the substrate.

公开(公告)号：US10103034B2

公开(公告)日：2018-10-16

申请号：US15678134

申请日：2017-08-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Li-Chieh Hsu ,  Fu-Shou Tsai ,  Yu-Ting Li ,  Yi-Liang Liu ,  Kun-Ju Li

IPC: H01L21/3105 ,  H01L29/06 ,  H01L29/78

Abstract: A method of planarizing a substrate surface is disclosed. A substrate having a major surface of a material layer is provided. The major surface of the material layer comprises a first region with relatively low removal rate and a second region of relatively high removal rate. A photoresist pattern is formed on the material layer. The photoresist pattern masks the second region, while exposes at least a portion of the first region. At least a portion of the material layer not covered by the photoresist pattern is etched away. A polish stop layer is deposited on the material layer. A cap layer is deposited on the polish stop layer. A chemical mechanical polishing (CMP) process is performed to polish the cap layer.

公开(公告)号：US20180138125A1

公开(公告)日：2018-05-17

申请号：US15853978

申请日：2017-12-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kun-Ju Li ,  Kuo-Chin Hung ,  Min-Chuan Tsai ,  Wei-Chuan Tsai ,  Yi-Han Liao ,  Chun-Tsen Lu ,  Fu-Shou Tsai ,  Li-Chieh Hsu

IPC: H01L23/528 ,  H01L29/417 ,  H01L23/532 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/5283 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76883 ,  H01L23/485 ,  H01L23/5228 ,  H01L23/53238 ,  H01L23/53266 ,  H01L29/41758 ,  H01L29/66628 ,  H01L29/7833

Abstract: A layout structure including a conductive structure is provided. The layout structure includes a dielectric layer formed on a substrate and a conductive structure formed in the dielectric layer. And the conductive structure further includes a barrier layer, a metal layer formed within the barrier layer, and a high resistive layer sandwiched in between the barrier layer and the metal layer.

公开(公告)号：US20180012772A1

公开(公告)日：2018-01-11

申请号：US15678134

申请日：2017-08-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Li-Chieh Hsu ,  Fu-Shou Tsai ,  Yu-Ting Li ,  Yi-Liang Liu ,  Kun-Ju Li

IPC: H01L21/3105 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L21/31053 ,  H01L21/31055 ,  H01L29/0653 ,  H01L29/7851

Abstract: A method of planarizing a substrate surface is disclosed. A substrate having a major surface of a material layer is provided. The major surface of the material layer comprises a first region with relatively low removal rate and a second region of relatively high removal rate. A photoresist pattern is formed on the material layer. The photoresist pattern masks the second region, while exposes at least a portion of the first region. At least a portion of the material layer not covered by the photoresist pattern is etched away. A polish stop layer is deposited on the material layer. A cap layer is deposited on the polish stop layer. A chemical mechanical polishing (CMP) process is performed to polish the cap layer.

公开(公告)号：US09673053B2

公开(公告)日：2017-06-06

申请号：US14549529

申请日：2014-11-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Rung-Yuan Lee ,  Yu-Ting Li ,  Jing-Yin Jhang ,  Chen-Yi Weng ,  Jia-Feng Fang ,  Yi-Wei Chen ,  Wei-Jen Wu ,  Po-Cheng Huang ,  Fu-Shou Tsai ,  Kun-Ju Li ,  Wen-Chin Lin ,  Chih-Chien Liu ,  Chih-Hsun Lin ,  Chun-Yuan Wu

IPC: H01L21/306 ,  H01L21/28

CPC classification number: H01L21/30625 ,  H01L21/28123 ,  H01L21/32115 ,  H01L21/3212

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a first material layer on the substrate; forming a stop layer on the first material layer; forming a second material layer on the stop layer; and performing a planarizing process to remove the second material layer, the stop layer, and part of the first material layer for forming a gate layer.

公开(公告)号：US20220084878A1

公开(公告)日：2022-03-17

申请号：US17023391

申请日：2020-09-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Fu-Shou Tsai ,  Yang-Ju Lu ,  Yong-Yi Lin ,  Yu-Lung Shih ,  Ching-Yang Chuang ,  Ji-Min Lin ,  Kun-Ju Li

IPC: H01L21/768 ,  H01L21/8234 ,  H01L21/3105

Abstract: A fabricating method of transistors includes providing a substrate with numerous transistors thereon. Each of the transistors includes a gate structure. A gap is disposed between gate structures adjacent to each other. Later, a protective layer and a first dielectric layer are formed in sequence to cover the substrate and the transistors and to fill in the gap. Next, numerous buffering particles are formed to contact the first dielectric layer. The buffering particles do not contact each other. Subsequently, a second dielectric layer is formed to cover the buffering particles. After that, a first planarization process is performed to remove part of the first dielectric layer, part of the second dielectric layer and buffering particles by taking the protective layer as a stop layer, wherein a removing rate of the second dielectric layer is greater than a removing rate of the buffering particles during the first planarization process.

公开(公告)号：US11211471B1

公开(公告)日：2021-12-28

申请号：US17017666

申请日：2020-09-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Fu-Shou Tsai ,  Yong-Yi Lin ,  Yang-Ju Lu ,  Yu-Lung Shih ,  Ji-Min Lin ,  Ching-Yang Chuang ,  Kun-Ju Li

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/40

Abstract: The present invention discloses a metal gate process. A sacrificial nitride layer is introduced during the fabrication of metal gates. The gate height can be well controlled by introducing the sacrificial nitride layer. Further, the particle fall-on problem can be effectively solved.

公开(公告)号：US20190035794A1

公开(公告)日：2019-01-31

申请号：US16151323

申请日：2018-10-03

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Yu-Ting Li ,  Jen-Chieh Lin ,  Wen-Chin Lin ,  Po-Cheng Huang ,  Fu-Shou Tsai

IPC: H01L27/108

Abstract: A semiconductor IC structure includes a substrate including at least a memory cell region and a peripheral region defined thereon, a plurality of memory cells formed in the memory cell region, at least an active device formed in the peripheral region, a plurality of contact plugs formed in the memory cell region, and at least a bit line formed in the memory cell region. The contact plugs are physically and electrically connected to the bit line. More important, bottom surfaces of the contact plugs are lower a surface of the substrate.

公开(公告)号：US20180061656A1

公开(公告)日：2018-03-01

申请号：US15245194

申请日：2016-08-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Fu-Shou Tsai ,  Yu-Ting Li ,  Li-Chieh Hsu ,  Yi-Liang Liu ,  Kun-Ju Li ,  Po-Cheng Huang ,  Chien-Nan Lin

IPC: H01L21/3105 ,  H01L21/02 ,  H01L21/311 ,  H01L21/8234

CPC classification number: H01L21/31055 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02227 ,  H01L21/02271 ,  H01L21/31111 ,  H01L21/823431

Abstract: A method for forming a semiconductor structure includes following steps. A substrate is provided, and a semiconductor layer is formed on the substrate. Next, a SiN-rich pre-oxide layer is formed on the semiconductor layer. After forming the SiN-rich pre-oxide layer, an anneal treatment is performed to partially transfer the SiN-rich pre-oxide layer to form a SiN layer and a SiO layer. And the SiO layer is formed the on the SiN layer. Subsequently, a planarization process is performed to remove a portion of the SiO layer to expose the SiN layer.