公开(公告)号：US20150118836A1

公开(公告)日：2015-04-30

申请号：US14064722

申请日：2013-10-28

Applicant: United Microelectronics Corp.

Inventor： Ching-Ling Lin ,  Chih-Sen Huang ,  Jia-Rong Wu ,  Ching-Wen Hung ,  Po-Chao Tsao

IPC: H01L29/66 ,  H01L21/768

CPC classification number: H01L29/66545 ,  H01L21/28247 ,  H01L21/76834 ,  H01L21/76897 ,  H01L29/41791 ,  H01L29/66628 ,  H01L29/66795 ,  H01L29/7848

Abstract: A method of fabricating a semiconductor device is disclosed. Provided is a substrate having a dummy gate formed thereon, a spacer on a sidewall of the dummy gate and a first dielectric layer surrounding the spacer. The dummy gate is removed to form a gate trench. A gate dielectric layer and at least one work function layer is formed in the gate trench. The work function layer and the gate dielectric layer are pulled down, and a portion of the spacer is laterally removed at the same time to widen a top portion of the gate trench. A low-resistivity metal layer is formed in a bottom portion of the gate trench. A hard mask layer is formed in the widened top portion of the gate trench.

Abstract translation: 公开了制造半导体器件的方法。 提供了一种其上形成有虚拟栅极的基板，在虚拟栅极的侧壁上的间隔物和围绕间隔物的第一介电层。 去除伪栅极以形成栅极沟槽。 栅极介电层和至少一个功函数层形成在栅极沟槽中。 功函数层和栅介质层被下拉，并且间隔件的一部分同时被横向去除，以加宽栅沟槽的顶部。 在栅极沟槽的底部形成低电阻率金属层。 在栅沟槽的加宽的顶部形成有硬掩模层。

公开(公告)号：US20150118835A1

公开(公告)日：2015-04-30

申请号：US14062909

申请日：2013-10-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Ling Lin ,  Chih-Sen Huang ,  Po-Chao Tsao ,  Ching-Wen Hung ,  Jia-Rong Wu ,  Chien-Ting Lin

IPC: H01L21/768 ,  H01L29/66

CPC classification number: H01L29/66477 ,  H01L21/28247 ,  H01L21/76834 ,  H01L21/76897 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/7848

Abstract: A method for manufacturing a semiconductor device includes following steps. A substrate having at least a transistor embedded in an insulating material formed thereon is provided. The transistor includes a metal gate. Next, an etching process is performed to remove a portion of the metal gate to form a recess and to remove a portion of the insulating material to form a tapered part. After forming the recess and the tapered part of the insulating material, a hard mask layer is formed on the substrate to fill up the recess. Subsequently, the hard mask layer is planarized.

Abstract translation: 一种制造半导体器件的方法包括以下步骤。 提供了至少具有嵌入在其上形成绝缘材料的晶体管的衬底。 晶体管包括金属栅极。 接下来，进行蚀刻处理以去除金属栅极的一部分以形成凹部并且去除绝缘材料的一部分以形成锥形部分。 在形成凹部和绝缘材料的锥形部分之后，在基板上形成硬掩模层以填充凹部。 随后，硬掩模层被平坦化。

公开(公告)号：US09000483B2

公开(公告)日：2015-04-07

申请号：US13895367

申请日：2013-05-16

Applicant: United Microelectronics Corp.

Inventor： Shih-Fang Hong ,  Po-Chao Tsao

IPC: H01L31/0328 ,  H01L29/94 ,  H01L27/088

CPC classification number: H01L29/66795 ,  H01L27/0886 ,  H01L29/6653

Abstract: A semiconductor device includes a substrate, a first fin structure, an electrical contact structure and a gate structure. The first fin structure includes a horizontal fin structure extending along a first direction and a vertical fin structure extending along a second direction. The substrate has a first region and a second region. A portion of the horizontal fin structure and the vertical fin structure are disposed in the first region, and the electrical contact structure directly covers the horizontal fin structure and the vertical fin structure within the first region. The gate structure partially overlaps the horizontal fin structure within the second region.

Abstract translation: 半导体器件包括衬底，第一鳍结构，电接触结构和栅极结构。 第一翅片结构包括沿着第一方向延伸的水平翅片结构和沿着第二方向延伸的垂直翅片结构。 衬底具有第一区域和第二区域。 水平翅片结构和垂直翅片结构的一部分设置在第一区域中，并且电接触结构直接覆盖第一区域内的水平翅片结构和垂直翅片结构。 栅极结构部分地与第二区域内的水平翅片结构重叠。

公开(公告)号：US08921226B2

公开(公告)日：2014-12-30

申请号：US13740289

申请日：2013-01-14

Applicant: United Microelectronics Corp.

Inventor： Ching-Wen Hung ,  En-Chiuan Liou ,  Chih-Sen Huang ,  Po-Chao Tsao

IPC: H01L21/768

CPC classification number: H01L21/76816 ,  H01L21/28518 ,  H01L21/31144 ,  H01L21/76814 ,  H01L21/76855 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a semiconductor structure having at least a contact plug includes the following steps. At first, at least a transistor and an inter-layer dielectric (ILD) layer are formed on a substrate, and the transistor includes a gate structure and two source/drain regions. Subsequently, a cap layer is formed on the ILD layer and on the transistor, and a plurality of openings that penetrate through the cap layer and the ILD layer until reaching the source/drain regions are formed. Afterward, a conductive layer is formed to cover the cap layer and fill the openings, and a part of the conductive layer is further removed for forming a plurality of first contact plugs, wherein a top surface of a remaining conductive layer and a top surface of a remaining cap layer are coplanar, and the remaining cap layer totally covers a top surface of the gate structure.

Abstract translation: 形成至少具有接触插塞的半导体结构的方法包括以下步骤。 首先，在衬底上形成至少一个晶体管和层间电介质（ILD）层，并且晶体管包括栅极结构和两个源极/漏极区域。 随后，在ILD层和晶体管上形成覆盖层，并且形成穿过覆盖层和ILD层的多个开口直到到达源/漏区。 之后，形成导电层以覆盖盖层并填充开口，并且进一步去除导电层的一部分以形成多个第一接触塞，其中剩余导电层的顶表面和顶表面 剩余的盖层是共面的，剩余的盖层完全覆盖栅极结构的顶表面。

公开(公告)号：US08883621B2

公开(公告)日：2014-11-11

申请号：US13728611

申请日：2012-12-27

Applicant: United Microelectronics Corp.

Inventor： Chia-Jung Li ,  Po-Chao Tsao

IPC: H01L21/8238 ,  H01L21/336 ,  H01L29/49 ,  H01L29/78 ,  H01L27/06 ,  H01L21/8234

CPC classification number: H01L29/49 ,  H01L21/02057 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/82345 ,  H01L21/823842 ,  H01L21/82385 ,  H01L21/823864 ,  H01L27/0629 ,  H01L29/165 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7834 ,  H01L29/7848

Abstract: Provided is a semiconductor structure including a gate structure, a first spacer, and a second spacer. The gate structure is formed on a substrate and includes a gate material layer, a first hard mask layer disposed on the gate material layer, and a second hard mask layer disposed on the first hard mask layer. The first spacer is disposed on sidewalls of the gate structure. The second spacer is disposed adjacent to the first spacer. The etch rate of the first hard mask layer, the etch rate of the first spacer, and the etch rate of the second spacer are substantially the same and significantly smaller than the etch rate of the second hard mask layer in a rinsing solution.

Abstract translation: 提供了包括栅极结构，第一间隔物和第二间隔物的半导体结构。 栅极结构形成在基板上，包括栅极材料层，设置在栅极材料层上的第一硬掩模层和设置在第一硬掩模层上的第二硬掩模层。 第一间隔件设置在栅极结构的侧壁上。 第二间隔件邻近第一间隔件设置。 第一硬掩模层的蚀刻速率，第一间隔物的蚀刻速率和第二间隔物的蚀刻速率与漂洗溶液中的第二硬掩模层的蚀刻速率基本相同并显着小于第二硬掩模层的蚀刻速率。

公开(公告)号：US20140322883A1

公开(公告)日：2014-10-30

申请号：US14331229

申请日：2014-07-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming-Te Wei ,  Wen-Chen Wu ,  Lung-En Kuo ,  Po-Chao Tsao

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66689 ,  H01L21/823807 ,  H01L21/823828 ,  H01L21/823864 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/66636 ,  H01L29/7816 ,  H01L29/7834 ,  H01L29/7848

Abstract: A method for fabricating a metal-oxide semiconductor (MOS) transistor is disclosed. The method includes the steps of: providing a semiconductor substrate; forming a silicon layer on the semiconductor substrate; performing a first photo-etching process on the silicon layer for forming a gate pattern; forming an epitaxial layer in the semiconductor substrate adjacent to two sides of the gate pattern; and performing a second photo-etching process on the gate pattern to form a slot in the gate pattern while using the gate pattern to physically separate the gate pattern into two gates.

Abstract translation: 公开了一种用于制造金属氧化物半导体（MOS）晶体管的方法。 该方法包括以下步骤：提供半导体衬底; 在所述半导体衬底上形成硅层; 在硅层上进行第一光蚀刻工艺以形成栅极图案; 在与栅极图案的两侧相邻的半导体衬底中形成外延层; 以及对所述栅极图案执行第二光蚀刻处理以在所述栅极图案中形成槽，同时使用所述栅极图案将所述栅极图案物理分离成两个栅极。

公开(公告)号：US20140246730A1

公开(公告)日：2014-09-04

申请号：US13781761

申请日：2013-03-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Chih-Sen Huang ,  Po-Chao Tsao

IPC: H01L49/02

CPC classification number: H01L27/0629 ,  H01L27/0288 ,  H01L27/0738 ,  H01L28/20 ,  H01L28/24 ,  H01L29/7304

Abstract: An embedded resistor including a first interdielectric layer, a cap layer, a resistive layer and a cap film is provided. The first interdielectric layer is located on a substrate. The cap layer is located on the first interdielectric layer, wherein the cap layer has a trench. The resistive layer conformally covers the trench, thereby having a U-shaped cross-sectional profile. The cap film is located in the trench and on the resistive layer, or, an embedded thin film resistor including a first interdielectric layer, a cap layer and a bulk resistive layer is provided. The first interdielectric layer is located on a substrate. The cap layer is located on the first interdielectric layer, wherein the cap layer has a trench. The bulk resistive layer is located in the trench.

Abstract translation: 提供了包括第一介电层，盖层，电阻层和盖膜的嵌入式电阻器。 第一介电层位于衬底上。 盖层位于第一介电层上，其中盖层具有沟槽。 电阻层共形地覆盖沟槽，从而具有U形横截面轮廓。 盖膜位于沟槽和电阻层中，或者提供包括第一介电层，盖层和体电阻层的嵌入式薄膜电阻器。 第一介电层位于衬底上。 盖层位于第一介电层上，其中盖层具有沟槽。 体电阻层位于沟槽中。

公开(公告)号：US20140241027A1

公开(公告)日：2014-08-28

申请号：US13776589

申请日：2013-02-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Po-Chao Tsao ,  Shu-Ru Wang ,  Chia-Wei Huang ,  Chieh-Te Chen ,  Feng-Yi Chang ,  Chih-Sen Huang

IPC: G11C11/412

CPC classification number: G11C11/412 ,  H01L27/0207 ,  H01L27/1104

Abstract: A static random access memory unit cell layout structure is disclosed, in which a slot contact is disposed on one active area and another one across from the one. A static random access memory unit cell structure and a method of fabricating the same are also disclosed, in which, a slot contact is disposed on drains of a pull-up transistor and a pull-down transistor, and a metal-zero interconnect is disposed on the slot contact and a gate line of another pull-up transistor. Accordingly, there is not an intersection of vertical and horizontal metal-zero interconnects, and there is no place suffering from twice etching. Leakage junction due to stitch recess can be avoided.

Abstract translation: 公开了一种静态随机存取存储器单元布局结构，其中，槽触点设置在一个有源区上，另一个位于一个有源区上。 还公开了一种静态随机存取存储单元单元结构及其制造方法，其中，在上拉晶体管和下拉晶体管的漏极上设置一个槽触点，并且设置金属零互连 在槽触点和另一个上拉晶体管的栅极线上。 因此，没有垂直和水平的金属零互连，没有两次蚀刻的地方。 可以避免缝合凹陷引起的泄漏接头。

公开(公告)号：US20140103402A1

公开(公告)日：2014-04-17

申请号：US13649126

申请日：2012-10-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Chih-Sen Huang ,  Po-Chao Tsao

IPC: H01L21/768 ,  H01L29/78

CPC classification number: H01L21/76816 ,  H01L21/76807 ,  H01L23/485 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention provides a semiconductor structure including at least a contact plug. The structure includes a substrate, a transistor, a first ILD layer, a second ILD layer and a first contact plug. The transistor is disposed on the substrate and includes a gate and a source/drain region. The first ILD layer is disposed on the transistor and levels with a top surface of the gate. The second ILD layer is disposed on the first ILD layer. The first contact plug is disposed in the first ILD layer and the second ILD layer and includes a first trench portion and a first via portion, wherein a boundary of the first trench portion and a first via portion is higher than the top surface of the gate. The present invention further provides a method of making the same.

Abstract translation: 本发明提供至少包括接触插头的半导体结构。 该结构包括衬底，晶体管，第一ILD层，第二ILD层和第一接触插塞。 晶体管设置在衬底上并且包括栅极和源极/漏极区域。 第一ILD层设置在晶体管上并且与栅极的顶表面平齐。 第二ILD层设置在第一ILD层上。 第一接触插塞设置在第一ILD层和第二ILD层中，并且包括第一沟槽部分和第一通孔部分，其中第一沟槽部分和第一通孔部分的边界高于栅极的顶表面 。 本发明还提供了制备该方法的方法。

公开(公告)号：US20160197005A1

公开(公告)日：2016-07-07

申请号：US15072370

申请日：2016-03-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Chao Tsao ,  Lung-En Kuo ,  Chien-Ting Lin ,  Shih-Fang Tzou

IPC: H01L21/762 ,  H01L21/027 ,  H01L21/8234 ,  H01L21/308 ,  H01L21/3105

CPC classification number: H01L21/76224 ,  H01L21/0273 ,  H01L21/3086 ,  H01L21/31053 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/785

Abstract: The present invention provides a semiconductor structure including a substrate, at least one fin group and a plurality of sub-fin structures disposed on the substrate, wherein the fin group is disposed between two sub-fin structures, and a top surface of each sub-fin structure is lower than a top surface of the fin group; and a shallow trench isolation (STI) disposed in the substrate, wherein the sub-fin structures are completely covered by the shallow trench isolation.