公开(公告)号：US20170076995A1

公开(公告)日：2017-03-16

申请号：US14880693

申请日：2015-10-12

Applicant: United Microelectronics Corp.

Inventor： Yun-Tzu Chang ,  Shih-Min Chou ,  Kuo-Chih Lai ,  Ching-Yun Chang ,  Hsiang-Chieh Yen ,  Yen-Chen Chen ,  Yang-Ju Lu ,  Nien-Ting Ho ,  Chi-Mao Hsu

IPC: H01L21/8238

CPC classification number: H01L21/823842

Abstract: A method for modulating a work function of a semiconductor device having a metal gate structure including the following steps is provided. A first stacked gate structure and a second stacked gate structure having an identical structure are provided on a substrate. The first stacked gate structure and the second stacked gate structure respectively include a first work function metal layer of a first type. A patterned hard mask layer is formed. The patterned hard mask layer exposes the first work function metal layer of the first stacked gate structure and covers the first work function metal layer of the second stacked gate structure. A first gas treatment is performed to the first work function metal layer of the first stacked gate structure exposed by the patterned hard mask layer. A gas used in the first gas treatment includes nitrogen-containing gas or oxygen-containing gas.

Abstract translation: 提供了一种用于调制具有包括以下步骤的金属栅极结构的半导体器件的功函数的方法。 在基板上设置具有相同结构的第一堆叠栅极结构和第二堆叠栅极结构。 第一堆叠栅极结构和第二堆叠栅极结构分别包括第一类型的第一功函数金属层。 形成图案化的硬掩模层。 图案化的硬掩模层暴露第一堆叠栅极结构的第一功函数金属层并且覆盖第二堆叠栅极结构的第一功函数金属层。 对由图案化的硬掩模层暴露的第一堆叠栅极结构的第一功函数金属层进行第一气体处理。 在第一气体处理中使用的气体包括含氮气体或含氧气体。

公开(公告)号：US20220084878A1

公开(公告)日：2022-03-17

申请号：US17023391

申请日：2020-09-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Fu-Shou Tsai ,  Yang-Ju Lu ,  Yong-Yi Lin ,  Yu-Lung Shih ,  Ching-Yang Chuang ,  Ji-Min Lin ,  Kun-Ju Li

IPC: H01L21/768 ,  H01L21/8234 ,  H01L21/3105

Abstract: A fabricating method of transistors includes providing a substrate with numerous transistors thereon. Each of the transistors includes a gate structure. A gap is disposed between gate structures adjacent to each other. Later, a protective layer and a first dielectric layer are formed in sequence to cover the substrate and the transistors and to fill in the gap. Next, numerous buffering particles are formed to contact the first dielectric layer. The buffering particles do not contact each other. Subsequently, a second dielectric layer is formed to cover the buffering particles. After that, a first planarization process is performed to remove part of the first dielectric layer, part of the second dielectric layer and buffering particles by taking the protective layer as a stop layer, wherein a removing rate of the second dielectric layer is greater than a removing rate of the buffering particles during the first planarization process.

公开(公告)号：US11211471B1

公开(公告)日：2021-12-28

申请号：US17017666

申请日：2020-09-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Fu-Shou Tsai ,  Yong-Yi Lin ,  Yang-Ju Lu ,  Yu-Lung Shih ,  Ji-Min Lin ,  Ching-Yang Chuang ,  Kun-Ju Li

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/40

Abstract: The present invention discloses a metal gate process. A sacrificial nitride layer is introduced during the fabrication of metal gates. The gate height can be well controlled by introducing the sacrificial nitride layer. Further, the particle fall-on problem can be effectively solved.

公开(公告)号：US11139384B2

公开(公告)日：2021-10-05

申请号：US16561002

申请日：2019-09-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Chih Lai ,  Yun-Tzu Chang ,  Wei-Ming Hsiao ,  Nien-Ting Ho ,  Shih-Min Chou ,  Yang-Ju Lu ,  Ching-Yun Chang ,  Yen-Chen Chen ,  Kuan-Chun Lin ,  Chi-Mao Hsu

IPC: H01L29/43 ,  H01L29/51 ,  H01L29/40 ,  H01L29/49 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first region, a second region, a third region, and a fourth region; forming a tuning layer on the second region; forming a first work function metal layer on the first region and the tuning layer of the second region; forming a second work function metal layer on the first region, the second region, and the fourth region; and forming a top barrier metal (TBM) layer on the first region, the second region, the third region, and the fourth region.

公开(公告)号：US20200006514A1

公开(公告)日：2020-01-02

申请号：US16561002

申请日：2019-09-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Chih Lai ,  Yun-Tzu Chang ,  Wei-Ming Hsiao ,  Nien-Ting Ho ,  Shih-Min Chou ,  Yang-Ju Lu ,  Ching-Yun Chang ,  Yen-Chen Chen ,  Kuan-Chun Lin ,  Chi-Mao Hsu

IPC: H01L29/51 ,  H01L29/40 ,  H01L29/49

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first region, a second region, a third region, and a fourth region; forming a tuning layer on the second region; forming a first work function metal layer on the first region and the tuning layer of the second region; forming a second work function metal layer on the first region, the second region, and the fourth region; and forming a top barrier metal (TBM) layer on the first region, the second region, the third region, and the fourth region.

公开(公告)号：US20180331193A1

公开(公告)日：2018-11-15

申请号：US16044581

申请日：2018-07-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Min Chou ,  Yun-Tzu Chang ,  Wei-Ning Chen ,  Wei-Ming Hsiao ,  Chia-Chang Hsu ,  Kuo-Chih Lai ,  Yang-Ju Lu ,  Yen-Chen Chen ,  Chun-Yao Yang

IPC: H01L29/423 ,  H01L29/51 ,  H01L21/02 ,  H01L29/49 ,  H01L29/06 ,  H01L27/092 ,  H01L27/088 ,  H01L21/28 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8238

CPC classification number: H01L29/42356 ,  H01L21/02183 ,  H01L21/02244 ,  H01L21/02252 ,  H01L21/02255 ,  H01L21/28088 ,  H01L21/32134 ,  H01L21/762 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/823842 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/4966 ,  H01L29/511 ,  H01L29/518

Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes an isolation layer, a gate dielectric layer, a tantalum nitride layer, a tantalum oxynitride layer, an n type work function metal layer and a filling metal. The isolation layer is formed on a substrate, and the isolation layer has a first gate trench. The gate dielectric layer is formed in the first gate trench, the tantalum nitride layer is formed on the gate dielectric layer, and the tantalum oxynitride layer is formed on the tantalum nitride layer. The n type work function metal layer is formed on the tantalum oxynitride layer in the first gate trench, and the filling metal is formed on the n type work function metal layer in the first gate trench.

公开(公告)号：US09691704B1

公开(公告)日：2017-06-27

申请号：US15175299

申请日：2016-06-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Chih Lai ,  Chia-Chang Hsu ,  Nien-Ting Ho ,  Ching-Yun Chang ,  Yen-Chen Chen ,  Shih-Min Chou ,  Yun-Tzu Chang ,  Yang-Ju Lu ,  Wei-Ming Hsiao ,  Wei-Ning Chen

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/76 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L21/768 ,  H01L21/3213

CPC classification number: H01L23/528 ,  H01L21/32133 ,  H01L21/76816 ,  H01L21/7682 ,  H01L21/7685 ,  H01L21/76877 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/5329 ,  H01L23/53295

Abstract: A semiconductor structure comprises a first wire level, a second wire level and a via level. The first wire level comprises a first conductive feature. The second wire level is disposed on the first wire level. The second wire level comprises a second conductive feature and a third conductive feature. The via level is disposed between the first wire level and the second wire level. The via level comprises a via connecting the first conductive feature and the second conductive feature. There is a first air gap between the first conductive feature and the second conductive feature. There is a second air gap between the second conductive feature and the third conductive feature. The first air gap and the second air gap are linked.