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公开(公告)号：US20160351575A1
公开(公告)日：2016-12-01
申请号：US14793714
申请日：2015-07-07
Applicant: United Microelectronics Corp.
Inventor： Ching-Wen Hung , Wei-Cyuan Lo , Ming-Jui Chen , Chia-Lin Lu , Jia-Rong Wu , Yi-Hui Lee , Ying-Cheng Liu , Yi-Kuan Wu , Chih-Sen Huang , Yi-Wei Chen , Tan-Ya Yin , Chia-Wei Huang , Shu-Ru Wang , Yung-Feng Cheng
IPC: H01L27/11 , H01L21/768 , H01L21/8234 , H01L21/311 , H01L29/78 , H01L23/535
CPC classification number: H01L21/823871 , H01L21/31144 , H01L21/76802 , H01L21/76805 , H01L21/76877 , H01L21/76895 , H01L21/76897 , H01L21/823431 , H01L21/823475 , H01L21/823821 , H01L23/485 , H01L23/535 , H01L27/0922 , H01L27/1104 , H01L27/1108 , H01L29/7851 , H01L29/7853
Abstract: The present invention provides a semiconductor structure, including a substrate, a plurality of fin structures, a plurality of gate structures, a dielectric layer and a plurality of contact plugs. The substrate has a memory region. The fin structures are disposed on the substrate in the memory region, each of which stretches along a first direction. The gate structures are disposed on the fin structures, each of which stretches along a second direction. The dielectric layer is disposed on the gate structures and the fin structures. The contact plugs are disposed in the dielectric layer and electrically connected to a source/drain region in the fin structure. From a top view, the contact plug has a trapezoid shape or a pentagon shape. The present invention further provides a method for forming the same.
Abstract translation: 本发明提供一种半导体结构，其包括基板，多个翅片结构，多个栅极结构，电介质层和多个接触插塞。 衬底具有存储区域。 翅片结构设置在存储区域中的基板上，每个沿着第一方向延伸。 栅极结构设置在翅片结构上，每个翼结构沿着第二方向延伸。 电介质层设置在栅极结构和鳍结构上。 接触插头设置在电介质层中并电连接到鳍结构中的源极/漏极区域。 从顶部看，接触塞具有梯形或五边形。 本发明还提供了一种形成该方法的方法。
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公开(公告)号：US20160064327A1
公开(公告)日：2016-03-03
申请号：US14494607
申请日：2014-09-24
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Ching-Ling Lin , Chih-Sen Huang , Ching-Wen Hung , Jia-Rong Wu , Tsung-Hung Chang , Yi-Hui Lee , Yi-Wei Chen
IPC: H01L23/535 , H01L21/768
CPC classification number: H01L23/5283 , H01L21/76816 , H01L21/76829 , H01L21/76832 , H01L21/76897 , H01L21/823475 , H01L23/53261 , H01L23/53266 , H01L27/0629
Abstract: A semiconductor device is disclosed. The semiconductor device includes: a substrate; a first metal gate on the substrate; a first hard mask on the first metal gate; an interlayer dielectric (ILD) layer on top of and around the first metal gate; and a patterned metal layer embedded in the ILD layer, in which the top surface of the patterned metal layer is lower than the top surface of the first hard mask.
Abstract translation: 公开了一种半导体器件。 半导体器件包括：衬底; 基板上的第一金属栅极; 第一个金属门上的第一个硬掩模; 在第一金属栅极的顶部和周围的层间绝缘层（ILD）层; 以及嵌入ILD层中的图案化金属层，其中图案化金属层的顶表面比第一硬掩模的顶表面低。
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公开(公告)号：US12284812B2
公开(公告)日：2025-04-22
申请号：US18636306
申请日：2024-04-16
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Yu-Ping Wang , Chen-Yi Weng , Chin-Yang Hsieh , Yi-Hui Lee , Ying-Cheng Liu , Yi-An Shih , I-Ming Tseng , Jing-Yin Jhang , Chien-Ting Lin
Abstract: A semiconductor structure includes a substrate, a first dielectric layer on the substrate, a plurality of memory stack structures on the first dielectric layer, an insulating layer conformally covering the memory stack structures and the first dielectric layer, a second dielectric layer on the insulating layer and filling the spaces between the memory stack structures, a first interconnecting structure through the second dielectric layer, wherein a top surface of the first interconnecting structure is flush with a top surface of the second dielectric layer and higher than top surfaces of the memory stack structures, a third dielectric layer on the second dielectric layer, and a plurality of second interconnecting structures through the third dielectric layer, the second dielectric layer and the insulating layer on the top surfaces of the memory stack structures to contact the top surfaces of the memory stack structures.
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公开(公告)号：US20240357943A1
公开(公告)日：2024-10-24
申请号：US18760005
申请日：2024-06-30
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chiu-Jung Chiu , Ya-Sheng Feng , I-Ming Tseng , Yi-An Shih , Yu-Chun Chen , Yi-Hui Lee , Chung-Liang Chu , Hsiu-Hao Hu
Abstract: A method for fabricating semiconductor device includes the steps of forming an inter-metal dielectric (IMD) layer on a substrate, forming a trench in the IMD layer, forming a synthetic antiferromagnetic (SAF) layer in the trench, forming a metal layer on the SAF layer, planarizing the metal layer and the SAF layer to form a metal interconnection, and forming a magnetic tunneling junction (MTJ) on the metal interconnection.
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公开(公告)号：US20240032439A1
公开(公告)日：2024-01-25
申请号：US18373295
申请日：2023-09-27
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Chen-Yi Weng , Chin-Yang Hsieh , Yi-Hui Lee , Ying-Cheng Liu , Yi-An Shih , Jing-Yin Jhang , I-Ming Tseng , Yu-Ping Wang , Chien-Ting Lin , Kun-Chen Ho , Yi-Syun Chou , Chang-Min Li , Yi-Wei Tseng , Yu-Tsung Lai , JUN XIE
Abstract: A method of fabricating magnetoresistive random access memory, including providing a substrate, forming a bottom electrode layer, a magnetic tunnel junction stack, a top electrode layer and a hard mask layer sequentially on the substrate, wherein a material of the top electrode layer is titanium nitride, a material of the hard mask layer is tantalum or tantalum nitride, and a percentage of nitrogen in the titanium nitride gradually decreases from a top surface of top electrode layer to a bottom surface of top electrode layer, and patterning the bottom electrode layer, the magnetic tunnel junction stack, the top electrode layer and the hard mask layer into multiple magnetoresistive random access memory cells.
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Patent Agency Ranking
公开(公告)号：US11812669B2
公开(公告)日：2023-11-07
申请号：US17835986
申请日：2022-06-09
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Chen-Yi Weng , Chin-Yang Hsieh , Yi-Hui Lee , Ying-Cheng Liu , Yi-An Shih , Jing-Yin Jhang , I-Ming Tseng , Yu-Ping Wang , Chien-Ting Lin , Kun-Chen Ho , Yi-Syun Chou , Chang-Min Li , Yi-Wei Tseng , Yu-Tsung Lai , Jun Xie
Abstract: A magnetoresistive random access memory (MRAM), including a bottom electrode layer on a substrate, a magnetic tunnel junction stack on the bottom electrode layer, a top electrode layer on the magnetic tunnel junction stack, and a hard mask layer on said top electrode layer, wherein the material of top electrode layer is titanium nitride, a material of said hard mask layer is tantalum or tantalum nitride, and the percentage of nitrogen in the titanium nitride gradually decreases from the top surface of top electrode layer to the bottom surface of top electrode layer.
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公开(公告)号：US11508904B2
公开(公告)日：2022-11-22
申请号：US17308057
申请日：2021-05-05
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Chen-Yi Weng , Yi-Wei Tseng , Chin-Yang Hsieh , Jing-Yin Jhang , Yi-Hui Lee , Ying-Cheng Liu , Yi-An Shih , I-Ming Tseng , Yu-Ping Wang
Abstract: A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) on a substrate; forming a first liner on the MTJ; forming a second liner on the first liner; forming an inter-metal dielectric (IMD) layer on the MTJ, and forming a metal interconnection in the IMD layer, the second liner, and the first liner to electrically connect the MTJ. Preferably, the first liner and the second liner are made of different materials.
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公开(公告)号：US20220029087A1
公开(公告)日：2022-01-27
申请号：US16997922
申请日：2020-08-19
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Yu-Chun Chen , Yen-Chun Liu , Ya-Sheng Feng , Chiu-Jung Chiu , I-Ming Tseng , Yi-An Shih , Yi-Hui Lee , Chung-Liang Chu , Hsiu-Hao Hu
Abstract: A semiconductor device includes a substrate having a magnetic random access memory (MRAM) region and a logic region, a first metal interconnection on the MRAM region, a second metal interconnection on the logic region, a stop layer extending from the first metal interconnection to the second metal interconnection, and a magnetic tunneling junction (MTJ) on the first metal interconnection. Preferably, the stop layer on the first metal interconnection and the stop layer on the second metal interconnection have different thicknesses.
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公开(公告)号：US20210035620A1
公开(公告)日：2021-02-04
申请号：US16556170
申请日：2019-08-29
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Yu-Ping Wang , Chen-Yi Weng , Chin-Yang Hsieh , Yi-Hui Lee , Ying-Cheng Liu , Yi-An Shih , I-Ming Tseng , Jing-Yin Jhang , Chien-Ting Lin
Abstract: A method for forming a semiconductor structure is disclosed. A substrate having a logic device region and a memory device region is provided. A first dielectric layer is formed on the substrate. Plural memory stack structures are formed on the first dielectric layer on the memory device region. An insulating layer is formed and conformally covers the memory stack structures and the first dielectric layer. An etching back process is performed to remove a portion of the insulating layer without exposing any portion of the memory stack structures. After the etching back process, a second dielectric layer is formed on the insulating layer and completely fills the spaces between the memory stack structures.
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公开(公告)号：US20200227473A1
公开(公告)日：2020-07-16
申请号：US16279956
申请日：2019-02-19
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Yi-Hui Lee , I-Ming Tseng , Ying-Cheng Liu , Yi-An Shih , Yu-Ping Wang
Abstract: An MRAM structure includes a dielectric layer. A contact hole is disposed in the dielectric layer. A contact plug fills in the contact hole and protrudes out of the dielectric layer. The contact plug includes a lower portion and an upper portion. The lower portion fills in the contact hole. The upper portion is outside of the contact hole. The upper portion has a top side and a bottom side greater than the top side. The top side and the bottom side are parallel. The bottom side is closer to the contact hole than the top side. An MRAM is disposed on the contact hole and contacts the contact plug.
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