公开(公告)号：US20170170296A1

公开(公告)日：2017-06-15

申请号：US14964546

申请日：2015-12-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chueh-Yang Liu ,  Yu-Ying Lin ,  I-cheng Hu ,  Tien-I Wu ,  Yu-Shu Lin ,  Yu-Ren Wang

IPC: H01L29/66 ,  H01L21/324 ,  H01L21/311 ,  H01L29/78 ,  H01L21/02

CPC classification number: H01L21/02587 ,  H01L21/0217 ,  H01L21/02362 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/324 ,  H01L29/165 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848

Abstract: A manufacturing method of a semiconductor structure for improving quality of an epitaxial layer is provided in the present invention. The manufacturing method includes the following steps. A gate structure is formed on a semiconductor substrate, and two lightly doped regions are formed in the semiconductor substrate at two sides of the gate structure. A capping layer is formed on the gate structure and the lightly doped regions. Two epitaxial layers are formed at the two sides of the gate structure after the step of forming the capping layer. An oxide film formed on the lightly doped regions will influence the growth condition of the epitaxial layers. A removing process is performed to remove the oxide film on the lightly doped regions before the step of forming the capping layer so as to improve the quality of the epitaxial layers.

公开(公告)号：US09633904B1

公开(公告)日：2017-04-25

申请号：US15352528

申请日：2016-11-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Ying Lin ,  Chueh-Yang Liu ,  Yu-Ren Wang ,  Neng-Hui Yang

IPC: H01L21/336 ,  H01L21/8234 ,  H01L21/265 ,  H01L21/3065 ,  H01L29/66 ,  H01L21/306 ,  H01L29/167 ,  H01L29/08 ,  H01L21/02 ,  H01L29/78 ,  H01L29/165

CPC classification number: H01L21/823418 ,  H01L21/02636 ,  H01L21/02639 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/30608 ,  H01L21/3065 ,  H01L21/823425 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

Abstract: A method for manufacturing a semiconductor device with epitaxial structure includes following steps: A substrate including a plurality of gate structures formed thereon is provided, and a spacer is respectively formed on sidewalls of each gate structure. Next, a first etching process is performed to form a first recess respectively at two sides of the gate structures and followed by performing an ion implantation to the first recesses. After the ion implantation, a second etching process is performed to widen the first recesses to form widened first recesses and to form a second recess respectively at a bottom of each widened first recess. Then, an epitaxial structure is respectively formed in the widened first recesses and the second recesses.

公开(公告)号：US10446667B2

公开(公告)日：2019-10-15

申请号：US16404749

申请日：2019-05-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Ying Lin ,  Yi-Liang Ye ,  Sung-Yuan Tsai ,  Chun-Wei Yu ,  Yu-Ren Wang ,  Zhen Wu ,  Tai-Yen Lin

IPC: H01L21/00 ,  H01L29/66 ,  H01L21/768 ,  H01L21/3065 ,  H01L21/306 ,  H01L21/285 ,  H01L29/78 ,  H01L21/265 ,  H01L29/08 ,  H01L21/02 ,  H01L21/3115

Abstract: A method for fabricating semiconductor device includes the steps of: forming a first gate structure on a substrate; performing a first etching process to form a recess adjacent to the first gate structure; performing an ion implantation process to form an amorphous layer directly under the recess; performing a second etching process to remove the amorphous layer; and forming an epitaxial layer in the recess.

公开(公告)号：US20170243749A1

公开(公告)日：2017-08-24

申请号：US15049152

申请日：2016-02-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chueh-Yang Liu ,  Chun-Wei Yu ,  Yu-Ying Lin ,  Yu-Ren Wang

IPC: H01L21/28 ,  H01L29/66 ,  H01L21/8234

CPC classification number: H01L21/28185 ,  H01L21/28167 ,  H01L21/823462 ,  H01L29/51 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545

Abstract: A method of forming an oxide layer is provided in the present invention. The method includes the following steps. A first oxide layer is formed on a semiconductor substrate, and a quality enhancement process is then performed to etch the first oxide layer and densify the first oxide layer at the same time for forming a second oxide layer. The first oxide layer is etched and densified at the same time by a mixture of dilute hydrofluoric acid (DHF) and hydrogen peroxide (H2O2) in the quality enhancement process. The thickness of the second oxide layer may be reduced and the quality of the second oxide layer may be enhanced by the quality enhancement process at the same time.

公开(公告)号：US09741818B2

公开(公告)日：2017-08-22

申请号：US14964546

申请日：2015-12-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chueh-Yang Liu ,  Yu-Ying Lin ,  I-cheng Hu ,  Tien-I Wu ,  Yu-Shu Lin ,  Yu-Ren Wang

IPC: H01L21/336 ,  H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L21/311 ,  H01L21/324

CPC classification number: H01L21/02587 ,  H01L21/0217 ,  H01L21/02362 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/324 ,  H01L29/165 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848

Abstract: A manufacturing method of a semiconductor structure for improving quality of an epitaxial layer is provided in the present invention. The manufacturing method includes the following steps. A gate structure is formed on a semiconductor substrate, and two lightly doped regions are formed in the semiconductor substrate at two sides of the gate structure. A capping layer is formed on the gate structure and the lightly doped regions. Two epitaxial layers are formed at the two sides of the gate structure after the step of forming the capping layer. An oxide film formed on the lightly doped regions will influence the growth condition of the epitaxial layers. A removing process is performed to remove the oxide film on the lightly doped regions before the step of forming the capping layer so as to improve the quality of the epitaxial layers.

公开(公告)号：US09530886B1

公开(公告)日：2016-12-27

申请号：US14977602

申请日：2015-12-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Ying Lin ,  Chueh-Yang Liu ,  Yu-Ren Wang ,  Neng-Hui Yang

IPC: H01L27/01 ,  H01L27/12 ,  H01L31/0392 ,  H01L29/78 ,  H01L21/265 ,  H01L21/3065 ,  H01L21/306 ,  H01L21/02 ,  H01L29/165 ,  H01L29/66 ,  H01L29/167 ,  H01L29/08 ,  H01L21/8234

CPC classification number: H01L21/823418 ,  H01L21/02636 ,  H01L21/02639 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/30608 ,  H01L21/3065 ,  H01L21/823425 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

Abstract: A semiconductor device includes a substrate, a gate structure, a spacer, and a plurality of hyper-sigma (Σ) shaped epitaxial stressors. The substrate includes a first semiconductor material, and the hyper-Σ shaped epitaxial stressors include the first semiconductor material and a second semiconductor material. A lattice constant of the second semiconductor material is different from a lattice constant of the first semiconductor material. The hyper-Σ shaped epitaxial stressors respectively include a first portion, a second portion and a neck physically connecting the first portion and the second portion. The first portion includes a pair of first tips pointing toward the gate structure in a cross-sectional view. The second portion includes a pair of second tips pointing toward the gate structure in the cross-sectional view. The neck includes a first slanted surface in the first portion and a second slanted surface in the second portion.

Abstract translation: 半导体器件包括衬底，栅极结构，间隔物和多个超西格玛（Σ）形外延应力源。 所述基板包括第一半导体材料，并且所述超Σ形外延应力源包括所述第一半导体材料和第二半导体材料。 第二半导体材料的晶格常数与第一半导体材料的晶格常数不同。 超Σ形外延应力器分别包括物理地连接第一部分和第二部分的第一部分，第二部分和颈部。 第一部分包括在横截面视图中指向门结构的一对第一尖端。 第二部分包括在横截面视图中指向门结构的一对第二尖端。 颈部包括第一部分中的第一倾斜表面和第二部分中的第二倾斜表面。

公开(公告)号：US10381228B2

公开(公告)日：2019-08-13

申请号：US14631807

申请日：2015-02-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Ying Lin ,  Ted Ming-Lang Guo ,  Chin-Cheng Chien ,  Chih-Chien Liu ,  Hsin-Kuo Hsu ,  Chin-Fu Lin ,  Chun-Yuan Wu

IPC: H01L21/306 ,  H01L21/3065 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78

Abstract: An epitaxial process applying light illumination includes the following steps. A substrate is provided. A dry etching process and a wet etching process are performed to form a recess in the substrate, wherein an infrared light illuminates while the wet etching process is performed. An epitaxial structure is formed in the recess.

公开(公告)号：US20190221562A1

公开(公告)日：2019-07-18

申请号：US15880492

申请日：2018-01-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsu Ting ,  Yu-Ying Lin ,  Yen-Hsing Chen ,  Chun-Jen Chen ,  Chun-Wei Yu ,  Keng-Jen Lin ,  Yu-Ren Wang

IPC: H01L27/088 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/66

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/0653 ,  H01L29/66545

Abstract: A semiconductor device includes a semiconductor substrate, an isolation structure, a cladding layer, and a gate structure. The semiconductor substrate includes fin shaped structures. The isolation structure is disposed between the fin shaped structures. Each of the fin shaped structures includes a first portion disposed above a top surface of the isolation structure and a second portion disposed on the first portion. A width of the second portion is smaller than a width of the first portion. The cladding layer is disposed on the first portion and the second portion of each of the fin shaped structures. The cladding layer includes a curved surface. The gate structure is disposed straddling the fin shaped structures.

公开(公告)号：US20170309485A1

公开(公告)日：2017-10-26

申请号：US15137010

申请日：2016-04-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Ying Lin ,  Chueh-Yang Liu ,  Yu-Ren Wang ,  Chun-Wei Yu ,  Kuang-Hsiu Chen ,  Yi-Liang Ye ,  Hsu Ting ,  Neng-Hui Yang

IPC: H01L21/268 ,  H01L21/687 ,  H01L21/67 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/306 ,  H01L21/265 ,  H01L29/66

CPC classification number: H01L21/2686 ,  H01L21/02057 ,  H01L21/26513 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/67051 ,  H01L21/6708 ,  H01L21/67115 ,  H01L21/68785 ,  H01L29/0847 ,  H01L29/66575 ,  H01L29/66636 ,  H01L29/7834

Abstract: An apparatus for semiconductor wafer treatment includes a wafer holding unit configured to receive a single wafer, at least a solution supply unit configured to apply a solution onto the wafer and an irradiation unit configured to emit irradiation to the wafer. The irradiation unit further includes at least a plurality of first light sources configured to emit irradiation in FIR range and a plurality of second light sources configured to emit irradiation in UV range.

公开(公告)号：US20160314969A1

公开(公告)日：2016-10-27

申请号：US15166291

申请日：2016-05-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Ying Lin ,  Kuang-Hsiu Chen ,  Ted Ming-Lang Guo ,  Yu-Ren Wang

IPC: H01L21/02 ,  H01L21/76 ,  H01L21/265 ,  H01L21/3065 ,  H01L21/306 ,  H01L29/423 ,  H01L29/06

CPC classification number: H01L21/02636 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/283 ,  H01L21/30604 ,  H01L21/30608 ,  H01L21/3065 ,  H01L21/76 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/42356 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

Abstract: The present invention provides a method for forming a semiconductor structure, comprising: firstly, a substrate is provided, next, a first dry etching process is performed, to form a recess in the substrate. Afterwards, an ion implantation process is performed to a bottom surface of the recess, a wet etching process is then performed, to etch partial sidewalls of the recess, so as to form at least two tips on two sides of the recess respectively, and a second dry etching process is performed, to etch partial bottom surface of the recess, wherein after the second dry etching process is performed, a lower portion of the recess has a U-shaped cross section profile.

Abstract translation: 本发明提供一种形成半导体结构的方法，包括：首先提供衬底，然后进行第一干蚀刻工艺，以在衬底中形成凹陷。 之后，对凹部的底面执行离子注入工艺，然后执行湿蚀刻工艺，以蚀刻凹部的部分侧壁，从而分别在凹槽的两侧形成至少两个尖端，并且 进行第二干蚀刻工艺，以蚀刻凹部的部分底表面，其中在执行第二干蚀刻工艺之后，凹部的下部具有U形横截面轮廓。